An object of one embodiment of the present invention is to propose a memory device in which a period in which data is held is ensured and memory capacity per unit area can be increased. In the memory device of one embodiment of the present invention, bit lines are divided into groups, and word lines are also divided into groups. The word lines assigned to one group are connected to the memory cell connected to the bit lines assigned to the one group. Further, the driving of each group of bit lines is controlled by a dedicated bit line driver circuit of a plurality of bit line driver circuits. In addition, cell arrays are formed on a driver circuit including the above plurality of bit line driver circuits and a word line driver circuit. The driver circuit and the cell arrays overlap each other.

An object of one embodiment of the present invention is to propose a memory device in which a period in which data is held is ensured and memory capacity per unit area can be increased. In the memory device of one embodiment of the present invention, bit lines are divided into groups, and word lines are also divided into groups. The word lines assigned to one group are connected to the memory cell connected to the bit lines assigned to the one group. Further, the driving of each group of bit lines is controlled by a dedicated bit line driver circuit of a plurality of bit line driver circuits. In addition, cell arrays are formed on a driver circuit including the above plurality of bit line driver circuits and a word line driver circuit. The driver circuit and the cell arrays overlap each other.

Systems, methods, and apparatus including multi-direction conductive lines and staircase contacts for semiconductor devices. One memory device includes an array of vertically stacked memory cells, the array including: a vertical stack of horizontally oriented conductive lines, each conductive line comprising: a first portion extending in a first horizontal direction; and a second portion extending in a second horizontal direction at an angle to the first horizontal direction.

Systems, methods, and apparatus including multi-direction conductive lines and staircase contacts for semiconductor devices. One memory device includes an array of vertically stacked memory cells, the array including: a vertical stack of horizontally oriented conductive lines, each conductive line comprising: a first portion extending in a first horizontal direction; and a second portion extending in a second horizontal direction at an angle to the first horizontal direction.

A semiconductor device includes a substrate including a cell area having a first active region and a peripheral circuit area having a second active region, a direct contact contacting the first active region in the cell area, a bit line structure disposed on the direct contact, a capacitor structure electrically connected to the first active region, a gate structure disposed on the second active region in the peripheral circuit area, lower wiring layers disposed adjacent to the gate structure and electrically connected to the second active region, upper wiring layers disposed on the lower wiring layers, a wiring insulating layer disposed between the lower wiring layers and the upper wiring layers, and upper contact plugs connected to at least one of the lower wiring layers and the upper wiring layers and extending through the wiring insulating layer.

A semiconductor device includes a substrate including a cell area having a first active region and a peripheral circuit area having a second active region, a direct contact contacting the first active region in the cell area, a bit line structure disposed on the direct contact, a capacitor structure electrically connected to the first active region, a gate structure disposed on the second active region in the peripheral circuit area, lower wiring layers disposed adjacent to the gate structure and electrically connected to the second active region, upper wiring layers disposed on the lower wiring layers, a wiring insulating layer disposed between the lower wiring layers and the upper wiring layers, and upper contact plugs connected to at least one of the lower wiring layers and the upper wiring layers and extending through the wiring insulating layer.

A memory device can comprise an array of memory cells comprising a plurality of vertically stacked tiers of memory cells, a respective plurality of horizontal access lines coupled to each of the plurality of tiers, and a plurality of vertical sense lines coupled to each of the plurality of tiers. The array of memory cells can further comprise a plurality of multiplexors each coupled to a respective vertical sense line and configured to electrically couple the respective vertical sense line to a horizontal sense line. The memory device can also comprise a semiconductor under the array (SuA) circuitry, comprising a plurality of sense amplifiers, each sense amplifier coupled to a respective subset of the plurality of multiplexors.

A memory device can comprise an array of memory cells comprising a plurality of vertically stacked tiers of memory cells, a respective plurality of horizontal access lines coupled to each of the plurality of tiers, and a plurality of vertical sense lines coupled to each of the plurality of tiers. The array of memory cells can further comprise a plurality of multiplexors each coupled to a respective vertical sense line and configured to electrically couple the respective vertical sense line to a horizontal sense line. The memory device can also comprise a semiconductor under the array (SuA) circuitry, comprising a plurality of sense amplifiers, each sense amplifier coupled to a respective subset of the plurality of multiplexors.

Some embodiments include an integrated assembly. The integrated assembly includes active regions which each have a digit-line-contact-region between a pair of capacitor-contact-regions. The capacitor-contact-regions are arranged in a pattern such that six adjacent capacitor-contact-regions form a substantially rectangular configuration. Conductive redistribution material is coupled with the capacitor-contact-regions and extends upwardly and laterally outwardly from the capacitor-contact-regions. Upper surfaces of the conductive redistribution material are arranged in a pattern such that seven adjacent of the upper surfaces form a unit of a substantially hexagonal-close-packed configuration. Capacitors are coupled with the upper surfaces of the conductive redistribution material.

Some embodiments include an integrated assembly. The integrated assembly includes active regions which each have a digit-line-contact-region between a pair of capacitor-contact-regions. The capacitor-contact-regions are arranged in a pattern such that six adjacent capacitor-contact-regions form a substantially rectangular configuration. Conductive redistribution material is coupled with the capacitor-contact-regions and extends upwardly and laterally outwardly from the capacitor-contact-regions. Upper surfaces of the conductive redistribution material are arranged in a pattern such that seven adjacent of the upper surfaces form a unit of a substantially hexagonal-close-packed configuration. Capacitors are coupled with the upper surfaces of the conductive redistribution material.