An apparatus comprising an input to couple to a negative voltage source; and circuitry to detect whether the input has crossed a negative voltage threshold, wherein the circuitry comprises a first capacitor that is selectively coupled to the first input and a second capacitor that is selectively coupled to a second input coupled to a positive voltage source.

Devices and techniques for a storage backed memory package save trigger are disclosed herein. Data can be received via a first interface. The data is stored in a volatile portion of the memory package. Here, the memory package includes a second interface arranged to connect a host to a controller in the memory package. A reset signal can be received at the memory package via the first interface. The data stored in the volatile portion of the memory package can be saved to a non-volatile portion of the memory package in response to the reset signal.

A memory device may include a memory system and an energy storage device. Additionally, the energy storage device may supply a first power to the memory system when a second power from a power supply is eliminated or insufficient.

A memory module may include: a battery; a plurality of devices including a first memory, a second memory, and a controller; and a power management integrated circuit configured to adjust a level of a battery power, received from the battery, and configured to supply a power supply voltage to each of the plurality of devices.

A memory system includes: a first nonvolatile memory; a second volatile memory; a controller; a power control circuit configured to perform control such that a first voltage is applied to the first memory, the second memory, and the controller based on first power supplied from an external power supply; and a power storage device configured to supply second power to the power control circuit while the first power from the external power supply is interrupted. While the first power supplied from outside is interrupted, the power control circuit applies a second voltage based on the second power supplied from the power storage device to the first memory, the second memory, and the controller. The power control circuit stops the application of the second voltage to the second memory after the data is read from the second memory and before the data is written into the first memory.

A system includes a memory device and a processing device, operatively coupled to the memory device, the processing device to perform operations comprising: measuring one of a temperature voltage shift or a read bit error rate of fixed data stored in the memory device in response to detecting a power on of the memory device, the fixed data having been programmed in response to detecting a power loss; estimating an amount of time for which the memory device was powered off based on results of the measuring; and in response to the amount of time satisfying a threshold criterion, updating a value for a temporal voltage shift of a block family based on the amount of time.

A memory system includes a connector through which power for the memory system is to be supplied from an external device, a controller, a nonvolatile memory device, a power source circuit connected to the controller and the nonvolatile memory device by power lines through which power is supplied to the controller and the nonvolatile memory device, and a power source control circuit that receives a supply of power from the external device through the connector and supplies the power to the power control circuit. The power source control circuit is configured to detect using a divided voltage of a voltage of the power supplied thereto, that the voltage of the power supplied thereto is higher than a predetermined voltage and interrupt the power supplied to the power control circuit if the voltage of the power supplied thereto is higher than the predetermined voltage.

Systems and methods are disclosed, including rebuilding a logical-to-physical (L2P) data structure of a storage system subsequent to relocating assigned marginal group of memory cells of a memory array of the storage system, such as when resuming operation from a low-power state, including an asynchronous power loss (APL).

The present application discloses a semiconductor chip, an electronic device and an electrostatic discharge (ESD) protection method for an electronic device thereof. The semiconductor chip includes an operation electrical contact, a detection electrical contact, an ESD protection unit, and a logic circuit. The operation electrical contact receives an operation signal. The detection electrical contact receives a chip connection signal. The ESD protection unit is coupled to the operation electrical contact. The logic circuit is coupled to the detection electrical contact, and adjusts capacitance of the ESD protection unit according to a chip connection signal received by the detection electrical contact.

A memory system includes: a first nonvolatile memory; a second volatile memory; a controller; a power control circuit configured to perform control such that a first voltage is applied to the first memory, the second memory, and the controller based on first power supplied from an external power supply; and a power storage device configured to supply second power to the power control circuit while the first power from the external power supply is interrupted. While the first power supplied from outside is interrupted, the power control circuit applies a second voltage based on the second power supplied from the power storage device to the first memory, the second memory, and the controller. The power control circuit stops the application of the second voltage to the second memory after the data is read from the second memory and before the data is written into the first memory.