The present technology relates to an electronic device. According to the present technology, a memory device having improved verify accuracy may include a memory block including memory cells, a read and write circuit including a plurality of page buffers, a current sensing circuit configured to perform a verify operation of comparing sensing voltages with a reference voltage, and a control logic configured to control the current sensing circuit to perform the verify operation. The control logic controls performing a first verify operation on each of page buffer groups having a same logical group number, and performing a second verify operation on each of page buffer groups having a same physical group number, and the current sensing circuit outputs a verify pass signal in response to both results of the first verify operation and the second verify operation satisfying a pass criterion.

A neuromorphic hardware apparatus based on a resistive memory array includes a resistive memory array in which a plurality of synaptic resistor elements are arranged. Each synaptic resistor element is changed in its resistance value depending on a voltage pulse applied thereto and stores the resistance value for a predetermined time. The apparatus also includes a neuron circuit configured to receive an output signal from the resistive memory array and to output a voltage signal to another resistive memory array. The neuron circuit includes a temperature compensation unit, which compensates for an output voltage of the resistive memory array on the basis of an operating temperature of the resistive memory array. Even when a resistive memory array outputs an abnormal output depending on an operating temperature, by compensating a neuron circuit for an input value, it is possible to prevent an operation error from occurring.

A memory device, such as an MRAM memory, includes a memory array with a plurality of bit cells. The memory array is configured to store trimming information and store user data. A sense amplifier is configured to read the trimming information from the memory array, and a trimming register is configured to receive the trimming information from the sense amplifier. The sense amplifier is configured to receive the trimming information from the trimming register so as to operate in a trimmed mode for reading the user data from the memory array.

A ferroelectric memory circuit (100) includes: a memory cell (102), wherein a memory state (102s) of the memory cell (102) is switchable between a first memory state and a second memory state, the memory cell (102) further configured to output an electrical current (101) in response to receiving a readout voltage (103); and a sense circuit (104) configured to output an output voltage (105) based on the result of integrating the electrical current (101) output by the memory cell (102), wherein the output voltage (105) represents whether the memory state (102s) is the first memory state or the second memory state.

Disclosed herein is a sense amplifier. In one aspect, the sense amplifier includes a first pair of cross-coupled transistors and a second pair of cross-coupled transistors coupled to a first port and a second port of the sense amplifier. In one aspect, the sense amplifier includes a first access transistor coupled between a first input line and the first port. In one aspect, the sense amplifier includes a second access transistor coupled between a second input line and the second port. In one aspect, the first pair of cross-coupled transistors includes a first transistor and a second transistor cross-coupled with each other. In one aspect, a source electrode of the first transistor is directly coupled to the first input line, and a source electrode of the second transistor is directly coupled to the second input line.

Devices and methods for sensing a memory cell are described. The memory cell may include a ferroelectric memory cell. During a read operation, a first switching component may selectively couple a sense component with the memory cell based on a logic state stored on the memory cell to transfer a charge between the memory cell and the sense component. A second switching component, which may be coupled with the first switching component, may down convert a voltage associated with the charge to another voltage that is within an operation voltage of the sense component. The sense component may operate at a lower voltage than a voltage at which the memory cell operates to reduce power consumption in some cases.

An improved sensing circuit is disclosed that utilizes a bit line in an unused memory array to provide reference values to compare against selected cells in another memory array. A circuit that can perform a self-test for identifying bit lines with leakage currents about an acceptable threshold also is disclosed.

Broadly speaking, embodiments of the present techniques provide an amplification circuit comprising a sense amplifier and at least one Correlated Electron Switch (CES) configured to provide a signal to the sense amplifier. The sense amplifier outputs an amplified version of the input signal depending on the signal provided by the CES element. The signal provided by the CES element depends on the state of the CES material. The CES element provides a stable impedance to the sense amplifier, which may improve the reliability of reading data from the bit line, and reduce the number of errors introduced during the reading.

A non-volatile memory (NVM) includes at least one memory unit region, each including a memory array and having first memory cells in the odd columns and second memory cells in the even columns. Corresponding to each memory unit region, the NVM includes a multiplexer including first bit line decoders and second bit line decoders, a comparator circuit including a first input terminal and a second input terminal, and a bias generation circuit generating a bias voltage. When reading a data information from a first memory cell, a first output voltage of the first memory cell is sent to the first input terminal and the bias voltage is sent to the second input terminal. When reading a data information from a second memory cell, a second output voltage of the second memory cell is sent to the second input terminal and the bias voltage is sent to the first input terminal.

A read-out circuit and a read-out method for a three-dimensional memory, comprises a read reference circuit and a sensitive amplifier, the read reference circuit produces read reference current capable of quickly distinguishing reading low-resistance state unit current and reading high-resistance state unit current. The read reference circuit comprises a reference unit, a bit line matching module, a word line matching module and a transmission gate parasitic parameter matching module. With respect to the parasitic effect and electric leakage of the three-dimensional memory in the plane and vertical directions, the present invention introduces the matching of bit line parasite parameters, leakage current and transmission gate parasitic parameters into the read reference current, and introduces the matching of parasitic parameters of current mirror into the read current, thereby eliminating the phenomenon of pseudo reading and reducing the read-out time.