An optical synapse comprises a memristive device for non-volatile storage of a synaptic weight dependent on resistance of the device, and an optical modulator for volatile modulation of optical transmission in a waveguide. The memristive device and optical modulator are connected in control circuitry which is operable, in a write mode, to supply a programming signal to the memristive device to program the synaptic weight and, in a read mode, to supply an electrical signal, dependent on the synaptic weight, to the optical modulator whereby the optical transmission is controlled in a volatile manner in dependence on programmed synaptic weight.

A computer memory system includes an electro-optical chip, an electrical fanout chip electrically connected to an electrical interface of the electro-optical chip, and at least one dual in-line memory module (DIMM) slot electrically connected to the electrical fanout chip. A photonic interface of the electro-optical chip is optically connected to an optical link. The electro-optical chip includes at least one optical macro that converts outgoing electrical data signals into outgoing optical data signals for transmission through the optical link. The optical macro also converts incoming optical data signals from the optical link into incoming electrical data signals and transmits the incoming electrical data signals to the electrical fanout chip. The electrical fanout chip directs bi-directional electrical data communication between the electro-optical chip and a dynamic random access memory (DRAM) DIMM corresponding to the at least one DIMM slot.

Memory devices having electro-optical substrates are described herein. In one embodiment, a memory device includes a plurality of memories carried by an electro-optical substrate. The electro-optical substrate can include a circuit board and an optical routing layer on the circuit board. The memories can be (a) electrically coupled to the circuit board and (b) optically coupled to the optical routing layer. In some embodiments, the optical routing layer is a polymer waveguide.

A disclosed system may include (1) a memory package having a physical memory and optical circuitry, (2) a processor package, separate and distinct from the memory package, having at least one physical processor and additional optical circuitry, and (3) an optical medium communicatively coupling the optical circuitry of the memory package with the additional optical circuitry of the processor package. Various other systems, apparatuses, and methods are also disclosed.

In a modular memory system, a memory control component, first and second memory sockets and data buffer components are all mounted to the printed circuit board. The first and second memory sockets have electrical contacts to electrically engage counterpart electrical contacts of memory modules to be inserted therein, and each of the data buffer components includes a primary data interface electrically coupled to the memory control component, and first and second secondary data interfaces electrically coupled to subsets of the electrical contacts within the first and second memory sockets, respectively.

A memory device includes a computing-in-memory macro and a clock generating circuit. The computing-in-memory macro is configured to perform in-memory computing based on a first clock signal. The clock generating circuit is arranged within the computing-in-memory macro and configured to generate the first clock signal. A frequency of the first clock signal is modified according to a condition of the computing-in-memory macro to cause the first clock signal to conform to an operation speed of the in-memory computing.

Implementations described and claimed herein provide a high-capacity, high-bandwidth scalable storage device. The scalable storage device includes a layer stack including at least one memory layer and at least one optical control layer positioned adjacent to the memory layer. The memory layer includes a plurality of memory cells and the optical control layer is adapted to receive optically-encoded read/write signals and to effect read and write operations to the plurality of memory cells through an electrical interface.

Systems and methods for an optical ternary content addressable memory (TCAM) are provided. The optical TCAM implements a time-division multiplexing (TDM) based encoding scheme to encode each bit position of a search word in the time domain. Each bit position is associated with at least two time slots. The encoded optical signal comprising the search word is routed through one or more modulators configured to represent a respective TCAM stored word. If a mismatch between at least one bit position of the search word and at least one TCAM stored word occurs, a photodetector or photodetector array will detect light.

A semiconductor storing apparatus capable of performing continuous readout between multiple chips in high speed is provided. A NAND-type flash memory includes the stacked multiple chips. Each of the chips includes: a readout part performing the continuous readout; an output buffer part outputting data readout from the readout part to input/output bus synchronously with a clock signal; and a final page detecting part detecting if readout pages are the final pages of the chips. The output buffer part responds to a detecting result of the final pages under a condition of performing the continuous readout between the chips. After outputting the data of the final pages through a first output buffer with a large driving capability, outputs or holds the data of the final pages through a second output buffer with a little driving capability.

A semiconductor integrated circuit including first semiconductor chip and second semiconductor chip that are vertically stacked, wherein the first semiconductor chip includes a first column data driving circuit configured to transmit internal data to the second semiconductor chip in a DDR (double data rate) scheme based on an internal strobe signal, and a first column strobe signal driving circuit configured to generate first column strobe signals that are source-synchronized with first column data transmitted to the second semiconductor chip by the first column data driving circuit, based on the internal strobe signal, and transmit the first column strobe signals to the second semiconductor chip.