A chip part is provided that includes a substrate in which an element region and an electrode region are set, an insulating film (a first insulating film and a second insulating film) which is formed on the substrate and which selectively includes an internal concave/convex structure in the electrode region on a surface, a first connection electrode and a second connection electrode which include, at a bottom portion, an anchor portion entering the concave portion of the internal concave/convex structure and which include an external concave/convex structure on a surface on the opposite side and a circuit element which is disposed in the element region and which is electrically connected to the first connection electrode and the second connection electrode.

A damascene method for manufacturing a thin film resistor (TFR) module is provided. A pair of heads are formed spaced apart from each other. A dielectric region is deposited over the pair of heads, and an opening extending over both heads is formed in the dielectric region. A TFR layer is deposited over the dielectric region and extending into the opening to define a cup-shaped TFR layer structure including (a) a laterally-extending TFR element base conductively connected to both heads and (b) vertical ridges extending upwardly from the laterally-extending TFR element base. A high density plasma (HDP) ridge removal process is performed to remove or shorten the vertical ridges from the cup-shaped TFR layer structure, thereby defining a TFR element having removed or shorted vertical ridges. The removal or shortening of the vertical ridges may improve the temperature coefficient of resistance (TCR) characteristic of the TFR element.

A three-dimensional thermistor device and a manufacturing method thereof. The three-dimensional thermistor device comprising a thermistor array formed on a base layer extending in first and second directions. Where the thermistor array comprises: thermistor pattern layers and insulating layers stacked alternately on the base layer in a third direction; each thermistor pattern layer including a continuous electrically conductive first trace disposed along a first path extending in both the first and second directions, and each insulating layer including an electrically conductive first via extending through the insulating layer in the third direction to electrically connect the first traces to each other. Where successive electrical connections between the respective first vias on the stacked insulating layers and the respective first traces on the stacked thermistor layers form a continuous electrical first thermistor element extending in the first, second and third directions across multiple of the thermistor pattern layers.

A strain gauge includes a flexible substrate; a resistor formed of material including at least one from among chromium and nickel, on or above the substrate; and electrodes electrically coupled to the resistor. Each electrode includes a terminal section extending from a corresponding end portion from among end portions of the resistor; a first metallic layer formed of copper, a copper alloy, nickel, or a nickel alloy, on or above the terminal section; and a second metallic layer formed of material having better solder wettability than the first metallic layer, on or above the first metallic layer.

A semiconductor device includes a first terminal, a second terminal positioned away from the first terminal, a first resistive segment coupled between the first terminal and the second terminal, a third terminal positioned away from the first terminal and the second terminal, a second resistive segment coupled between the second terminal and third terminal, a first floating plate disposed physically proximate the first resistive segment and including a first end coupled to one of the first terminal and the second terminal, and a second floating plate disposed physically proximate the second resistive segment and including a first end coupled to one of the second terminal and the third terminal.

Aspects of the disclosure relate to apparatus and methods for producing a downhole electrical component, having steps of providing a non-conductive polymer substrate, establishing an active area on the non-conductive polymer substrate, patterning the active area on the non-conductive polymer substrate with a conductive material through an additive manufacturing process and incorporating the patterned non-conductive polymer substrate into a final arrangement.

Self-cooling semiconductor resistor and manufacturing method thereof are provided. The resistor comprises: multiple N-type and P-type wells in a semiconductor substrate, first polysilicon gates on each N-type well, second polysilicon gates on each P-type well, and metal interconnect layers. The multiple N-type and P-type wells are arranged alternately in row and column direction, respectively. N-type and P-type deep doped regions are formed on each N-type and P-type well, respectively. The first and second polysilicon gates are N-type and P-type deep doped respectively, and there is no gate oxide layer between the first and second polysilicon gates and the semiconductor substrate. The metal interconnect layers connect the multiple first and second polysilicon gates as an S-shaped structure. In the present application, the flow direction of heat is from the inside of the resistor to its surface, thereby realizing heat dissipation and cooling.

In some examples, a touch screen includes resistors between the touch electrodes and routing traces. In some examples, the resistors can include a transparent conductive material included in the touch electrodes of the touch screen. The resistors can be located in a border region of the touch screen that can surround an active area of the touch screen that can include the touch electrodes and display pixels of the touch screen, for example. In some examples, the resistors included in the touch screen can have different resistances from each other and the same outer dimensions as one another. The resistors can reduce the variation in resistance from channel to channel in the touch screen, which can improve touch screen performance, for example.

A method is provided for forming a thin film resistor (TFR) in an integrated circuit (IC) device. A TFR film is formed and annealed over an IC structure including IC elements and IC element contacts. At least one TFR cap layer is formed, and a TFR etch defines a TFR element from the TFR film. A TFR contact etch forms TFR contact openings over the TFR element, and a metal layer is formed over the IC structure and extending into the TFR contact openings to form metal contacts to the IC element contacts and the TFR element. The TFR cap layer(s), e.g., SiN cap and/or oxide cap formed over the TFR film, may (a) provide an etch stop during the TFR contact etch and/or (b) provide a hardmask during the TFR etch, which may eliminate the use of a photomask and thereby eliminate post-etch removal of photomask polymer.

An electronic component of the present disclosure includes a first insulating layer that includes impurities, a thin film resistor formed on the first insulating layer, and a barrier layer that is formed in at least one part of a region between the thin film resistor and the first insulating layer and that obstructs transmission of the impurities. The first insulating layer includes a first surface and a concave portion that is hollowed with respect to the first surface, and the barrier layer may include a first part embedded in the concave portion and a second part formed along the first surface of the first insulating layer from an upper area of the first part.