In an embodiment a ceramic material includes ZnO as main constituent, Y as a first additive, second additives including at least one compound containing a metal element, wherein the metal element is selected from the group consisting of Bi, Cr, Co, Mn, Ni and Sb, Si.sup.4+ as a first dopant and second dopants having at least one compound containing a metal cation from Al.sup.3+, B.sup.3+, or Ba.sup.2+, wherein a corresponds to a molar proportion of Bi calculated as Bi.sub.2O.sub.3, b corresponds to a molar proportion of Y calculated as Y.sub.2O.sub.3, c corresponds to a molar proportion of Al calculated as Al.sub.2O.sub.3, d corresponds to a molar proportion of Ba calculated as BaO, e corresponds to a molar proportion of B calculated as B.sub.2O.sub.3, f corresponds to a molar proportion of Si calculated as SiO.sub.2, g corresponds to a molar proportion of Ni calculated as NiO, h corresponds to a molar proportion of Co calculated as Co.sub.3O.sub.4, i corresponds to a molar proportion of Cr calculated as Cr.sub.2O.sub.3, j corresponds to a molar proportion of Sb calculated as Sb.sub.2O.sub.3, and k corresponds to a molar proportion of Mn calculated as Mn.sub.3O.sub.4.

A three-dimensional thermistor device and a manufacturing method thereof. The three-dimensional thermistor device comprising a thermistor array formed on a base layer extending in first and second directions. Where the thermistor array comprises: thermistor pattern layers and insulating layers stacked alternately on the base layer in a third direction; each thermistor pattern layer including a continuous electrically conductive first trace disposed along a first path extending in both the first and second directions, and each insulating layer including an electrically conductive first via extending through the insulating layer in the third direction to electrically connect the first traces to each other. Where successive electrical connections between the respective first vias on the stacked insulating layers and the respective first traces on the stacked thermistor layers form a continuous electrical first thermistor element extending in the first, second and third directions across multiple of the thermistor pattern layers.

In an embodiment a method for manufacturing a multilayer varistor includes providing a first ceramic powder for producing a first ceramic material and at least one second ceramic powder for producing a second ceramic material, wherein the ceramic powders differ from each other in concentration of monovalent elements X.sup.+ by 50 ppm≤Δc(X.sup.+)≤5000 ppm, wherein X.sup.+=(Li.sup.+, Na.sup.+, K.sup.+ or Ag.sup.+), and wherein Δc denotes a maximum concentration difference occurring between an active region and a near-surface region of the multilayer varistor, slicking of the ceramic powders and forming of green films, partially printing of a part of the green films with a metal paste to form inner electrodes, stacking printed and unprinted green films, laminating, decarbonizing and sintering the green films and applying outer electrodes.

In an embodiment a method for manufacturing a multilayer varistor includes providing a first ceramic powder for producing a first ceramic material and at least one second ceramic powder for producing a second ceramic material, wherein the ceramic powders differ from each other in concentration of monovalent elements X.sup.+ by 50 ppm≤Δc(X.sup.+)≤5000 ppm, wherein X.sup.+=(Li.sup.+, Na.sup.+, K.sup.+ or Ag.sup.+), and wherein Δc denotes a maximum concentration difference occurring between an active region and a near-surface region of the multilayer varistor, slicking of the ceramic powders and forming of green films, partially printing of a part of the green films with a metal paste to form inner electrodes, stacking printed and unprinted green films, laminating, decarbonizing and sintering the green films and applying outer electrodes.

A multilayer device and a method for producing a multilayer device are disclosed. In an embodiment a multilayer device includes a main body having at least two external electrodes, at least one first internal electrode; at least one second internal electrode, wherein each internal electrode is electrically conductively connected to an external electrode, a plurality of ceramic layers, wherein the ceramic layers comprise the internal electrodes and at least one dielectric layer, wherein, viewed along a stack direction of the ceramic layers, the dielectric layer being arranged between the internal electrodes, and wherein the dielectric layer is printed onto at least one sub-region of one of the ceramic layers.

A complex device is provided. A complex device according to an embodiment of the present invention comprises: a suppressor including a pair of first dielectric sheet layers having a first dielectric constant and a pair of internal electrodes spaced apart from each other on one surface of one of the pair of first dielectric sheet layers; a capacitor including a plurality of second dielectric sheet layers having a second dielectric constant and a plurality of capacitor electrodes provided on each of the plurality of second dielectric sheet layers; and a pair of external terminals provided on both sides of the suppressor and the capacitor to be connected to the plurality of capacitor electrodes and the pair of internal electrodes. Here, provided is the complex device in which the first dielectric constant is greater than the second dielectric constant.

A resistor circuit, an artificial intelligence chip and a method for manufacturing the same are provided. The resistor circuit includes a stack structure. The stack structure includes resistive material layers and insulating layers stacked alternately. The resistor circuit includes at least two unit resistors electrically connected in series or parallel. The at least two unit resistors are respectively defined in the resistive material layers of different layers.

A resistor circuit, an artificial intelligence chip and a method for manufacturing the same are provided. The resistor circuit includes a stack structure. The stack structure includes resistive material layers and insulating layers stacked alternately. The resistor circuit includes at least two unit resistors electrically connected in series or parallel. The at least two unit resistors are respectively defined in the resistive material layers of different layers.

A multilayer chip varistor includes an element body, first and second external electrodes, and first and second electrical conductor groups. The first electrical conductor group includes a first internal electrode connected to the first external electrode, and a first intermediate electrical conductor opposed to the first internal electrode. The second electrical conductor group includes a second internal electrode including a first electrically conductive material and connected to the second external electrode, and a second intermediate electrical conductor opposed to the second internal electrode. At least one of the first and second intermediate electrical conductors includes the second electrically conductive material. The element body includes a low electrical resistance region between the first and second internal electrodes. The second electrically conductive material is diffused in the low electrical resistance region.

A multilayer chip varistor includes an element body, first and second external electrodes, and first and second electrical conductor groups. The first electrical conductor group includes a first internal electrode connected to the first external electrode, and a first intermediate electrical conductor opposed to the first internal electrode. The second electrical conductor group includes a second internal electrode including a first electrically conductive material and connected to the second external electrode, and a second intermediate electrical conductor opposed to the second internal electrode. At least one of the first and second intermediate electrical conductors includes the second electrically conductive material. The element body includes a low electrical resistance region between the first and second internal electrodes. The second electrically conductive material is diffused in the low electrical resistance region.