A multilayer ceramic electronic component includes a ceramic body including first and second internal electrodes disposed to face each other and a dielectric layer interposed therebetween. When an average thickness of the dielectric layer is denoted as ‘td,’ an average thickness of the first and second internal electrodes is denoted as ‘te,’ and a standard deviation of thicknesses of an internal electrode, measured at a plurality of points in a predetermined region of the internal electrode, is denoted as ‘σte,’ a ratio of the standard deviation of thicknesses of the internal electrode to the average thickness of the dielectric layer, which is denoted as ‘σte/td,’ satisfies 0.12≤σte/td≤0.21.

A multilayer electronic device may include a plurality of dielectric layers stacked in a Z-direction that is perpendicular to an X-Y plane. The device may include a first conductive layer overlying one of the plurality of dielectric layers. The multilayer electronic device may include a second conductive layer overlying another of the plurality of dielectric layers and spaced apart from the first conductive layer in the Z-direction. The second conductive layer may overlap the first conductive layer in the X-Y plane at an overlapping area to form a capacitor. The first conductive layer may have a pair of parallel edges at a boundary of the overlapping area and an offset edge within the overlapping area that is parallel with the pair of parallel edges. An offset distance between the offset edge and at least one of the pair of parallel edges may be less than about 500 microns.

A chip component includes a substrate that has a first surface and a second surface on a side opposite to the first surface, a plurality of wall portions that are formed on a side of the first surface by using a part of the substrate, that have one end portion and one other end portion, and that are formed of a plurality of pillar units, a support portion that is formed around the wall portions by using a part of the substrate and that is connected to at least one of the end portion and the other end portion of the wall portions, and a capacitor portion formed by following a surface of the wall portion, in which each of the pillar units includes a central portion and three convex portions that extend from the central portion in three mutually different directions in a plan view and in which the wall portion is formed by a connection between the convex portions of the pillar units that adjoin each other.

A film capacitor includes first and second contact layers and a metallized dielectric film with first and second end faces and with first and second film sides. The first end face of the metallized dielectric film is connected to the first contact layer and the second end face is connected to the second contact layer. The metallized dielectric film has first, second and third metallization layers, with at least two of the metallization layers applied on the first film side of the metallized dielectric film and at least a further of the metallization layers applied on the second film side. The metallization layers are arranged on the film sides in such a manner that a first overlap with a first partial capacitance and a second overlap with a second partial capacitance are embodied between the metallization layers on the film sides, with the partial capacitances forming a series connection.

An electronic component includes a multilayer body including a multilayer main body including end surfaces at which internal nickel electrode layers are exposed, side gap portions, external nickel layers on the end surfaces of the multilayer body, and external copper electrode layers covering the end surfaces on which the external nickel layers are provided. A nickel-based oxide and/or a silicon-based oxide are provided between the external nickel layer and the external copper electrode layer. A nickel layer and a tin layer are provided outside the external copper electrode layer. In a cross section passing through a middle of the electronic component in the width direction and extending in the length direction and the lamination direction, a relationship of about 0.2≤Tea/Tem≤about 1.1 is satisfied.

A method for manufacturing a capacitive device comprising the following steps: i) provide a substrate comprising: a first area made of a first material and/or having a first texture, a second area made of a second material and/or having a second texture, a third area made of a third material and/or having a third texture, ii) make nanopillars grow over the substrate with which a nanopillar layer is obtained locally having different densities, the density of the first area being lower than the density of the third area, iii) deposit an insulating layer, iv) deposit a conductive layer, with which a capacitive stack is formed at the first area, the capacitive stack comprising the insulating layer and the conductive layer.

An embodiment of the present disclosure provides a MIM capacitor by High-k dielectric and method for fabricating the same to prevent formation of oxygen-based interface films between a lower electrode and a dielectric layer, and between an upper electrode and a dielectric layer by stacking a first film formed of metal between the dielectric layer formed of a High-k material having a high dielectric constant and the lower electrode formed of metal, and a second film formed of metal between the dielectric layer and the upper electrode.

A capacitor that can make a failure mode into an open mode even when a short circuit caused by insulation breakdown occurs in a dielectric layer is provided. The capacitor includes: a substrate; an MIM structure disposed on the Substrate, the MIM structure including a dielectric layer, a bottom electrode layer disposed on one side of the dielectric layer and composed of a first conductive material, and a top electrode layer disposed on the other side of the dielectric layer; a first external electrode disposed on the substrate; a second external electrode disposed on the substrate; and a connection conductor connecting between the bottom electrode layer and the first external electrode, the connection conductor including a first contact portion contacting the substrate.

Glass substrates having transverse capacitors for use with semiconductor packages and related methods are disclosed. An example semiconductor package includes a glass substrate having a through glass via between a first surface and a second surface opposite the first surface. A transverse capacitor is located in the through glass via. The transverse capacitor includes a dielectric material positioned in a first portion of the through glass via, a first barrier/seed layer positioned in a second portion of the through glass via, and a first conductive material positioned in a third portion of the through glass via.

A multilayer capacitor includes a capacitor body including first to sixth surface, and including a plurality of dielectric layers, and first and second internal electrodes; and first and second external electrodes. The first and second internal electrodes include first and second capacitance forming portion, first and second lead-out portion extending from the first and second capacitance forming portion toward the third surface of the capacitor body and connected to the first and second external electrode, and first and second dot pattern portion formed in at least one corner of the first and second capacitance forming portion. The first dot pattern portion and the second dot pattern portion have dot patterns not overlapping each other in the first direction.