A trench capacitor manufacturing method is provided. The method includes forming a deep trench in a wafer, forming a trench capacitor structure including a plurality of dielectric films and a plurality of conductive layers in the deep trench; determining if the wafer has a tensile stress based on the forming of the trench capacitor structure; performing a high temperature heat treatment to the trench capacitor structure to change a form of the wafer to a direction that offsets the tensile stress; forming an inter-layer insulating film on the trench capacitor structure; and forming a metal interconnect on the inter-layer insulating film.

A chip component includes a substrate that has a first surface and a second surface on a side opposite to the first surface, a plurality of wall portions that are formed on a side of the first surface by using a part of the substrate, that have one end portion and one other end portion, and that are formed of a plurality of pillar units, a support portion that is formed around the wall portions by using a part of the substrate and that is connected to at least one of the end portion and the other end portion of the wall portions, and a capacitor portion formed by following a surface of the wall portion, in which each of the pillar units includes a central portion and three convex portions that extend from the central portion in three mutually different directions in a plan view and in which the wall portion is formed by a connection between the convex portions of the pillar units that adjoin each other.

A ceramic electronic component includes a multilayer chip having a substantially rectangular parallelepiped shape and including a first multilayer structure and a second multilayer structure disposed on each of top and bottom faces of the first multilayer structure, the first multilayer structure including first ceramic dielectric layers having a first width in a first direction in which side faces of the multilayer chip are opposite to each other, the second multilayer structure including second internal electrode layers having a second width less than the first width in the first direction, and a pair of external electrodes formed from the respective two edge faces to at least one of side faces of the multilayer chip, wherein main components of the first and second internal electrode layers differ from a main component of the external electrodes.

Embodiments described herein may be related to apparatuses, processes, and techniques related to creating capacitors at the interface of a glass substrate. These capacitors may be three-dimensional (3-D) capacitors formed using trenches within the glass core of the substrate using laser-assisted etching techniques. A first electrode may be formed on the glass, including on the surface of trenches or other features etched in the glass, followed by a deposition of a dielectric material or a capacitive material. A second electrode may then be formed on top of the dielectric material. Other embodiments may be described and/or claimed.

A ceramic electronic device includes: a multilayer chip in which each of internal electrode layers and each of dielectric layers are alternately stacked, wherein the multilayer chip has a first capacity region having a first electrostatic capacity C.sub.1 and a first inductance L.sub.1 and a second capacity region having a second electrostatic capacity C.sub.2 and a second inductance L.sub.2, wherein the first electrostatic capacity C.sub.1, the first inductance L.sub.1, the second electrostatic capacity C.sub.2 and the second inductance L.sub.2 satisfy (C.sub.1.Math.L.sub.1)/(C.sub.2.Math.L.sub.2)<0.5 or 1.9<(C.sub.1.Math.L.sub.1)/(C.sub.2.Math.L.sub.2).

A capacitor that can make a failure mode into an open mode even when a short circuit caused by insulation breakdown occurs in a dielectric layer is provided. The capacitor includes: a substrate; an MIM structure disposed on the Substrate, the MIM structure including a dielectric layer, a bottom electrode layer disposed on one side of the dielectric layer and composed of a first conductive material, and a top electrode layer disposed on the other side of the dielectric layer; a first external electrode disposed on the substrate; a second external electrode disposed on the substrate; and a connection conductor connecting between the bottom electrode layer and the first external electrode, the connection conductor including a first contact portion contacting the substrate.

A capacitor structure and a power converter are provided. The capacitor structure includes a parallel cell combination, and the parallel cell combination includes a plurality of cells and a plurality of current collectors. In the parallel cell combination: the cells are connected in parallel, and the poles connected in parallel are respectively connected with other devices through corresponding confluence points. Same poles of two adjacent cells are connected through a corresponding current collector, and the current-carrying specifications of each current collector is lower than the current-carrying requirements of a confluence point of a corresponding pole. That is to say, a conductor that implements the parallel connection of the cells is no longer a whole copper plate, but the individual current collectors, thus realizing the reduction of the cost of the conductor material.

A capacitor according to an embodiment includes a substrate having a first surface and a second surface and provided with one or more first through holes each extending from the first surface to the second surface, a first conductive layer covering the first surface, the second surface, and side walls of the one or more first through holes, a second conductive layer facing the first surface, the second surface, and the side walls of the one or more first through holes, with the first conductive layer interposed therebetween, and a dielectric layer interposed between the first conductive layer and the second conductive layer.

A semiconductor package structure includes a substrate, a redistribution layer, a first semiconductor die, and a first capacitor. The substrate has a wiring structure. The redistribution layer is disposed over the substrate. The first semiconductor die is disposed over the redistribution layer. The first capacitor is disposed in the substrate and is electrically coupled to the first semiconductor die. The first capacitor includes a first capacitor substrate, a plurality of first capacitor cells, and a first through via. The first capacitor substrate has a first top surface and a first bottom surface. The first capacitor cells are disposed in the first capacitor substrate. The first through via is disposed in the first capacitor substrate and electrically couples the first capacitor cells to the wiring structure on the first top surface and the first bottom surface.

A method of capacitance structure manufacturing includes following operations. A plurality of insulating tubes is formed over a substrate and perpendicular to the substrate. A first supporting layer and a second supporting layer above the first supporting layer are formed and connect the insulating tubes. The first supporting layer protrudes from the second supporting layer. Conductive material is filled in the insulating tubes to form rod capacitors forming a capacitor array and the capacitor array is covered by an oxide layer from its top to the substrate. The oxide layer is formed along the first supporting layer and the second supporting layer such that the oxide layer extends along a direction having an angle with respect to the substrate.