H01J21/10

Gate all around vacuum channel transistor
11664458 · 2023-05-30 · ·

A vacuum channel transistor having a vertical gate-all-around (GAA) architecture provides high performance for high-frequency applications, and features a small footprint compared with existing planar devices. The GAA vacuum channel transistor features stacked, tapered source and drain regions that are formed by notching a doped silicon pillar using a lateral oxidation process. A temporary support structure is provided for the pillar during formation of the vacuum channel. Performance of the GAA vacuum channel transistor can be tuned by replacing air in the channel with other gases such as helium, neon, or argon. A threshold voltage of the GAA vacuum channel transistor can be adjusted by altering dopant concentrations of the silicon pillar from which the source and drain regions are formed.

VACUUM TUNNELING DEVICE AND METHOD OF MANUFACTURING THE SAME

A method of manufacturing a vacuum tunneling device, the method including forming a tunnelling device on a substrate; forming an insulating interlayer on the substrate such that the insulating interlayer has an opening exposing the tunneling device; and performing a gradient deposition process in a vacuum chamber to form a sealing layer on the insulating interlayer such that the sealing layer fills an upper portion of the opening.

VACUUM TUNNELING DEVICE AND METHOD OF MANUFACTURING THE SAME

A method of manufacturing a vacuum tunneling device, the method including forming a tunnelling device on a substrate; forming an insulating interlayer on the substrate such that the insulating interlayer has an opening exposing the tunneling device; and performing a gradient deposition process in a vacuum chamber to form a sealing layer on the insulating interlayer such that the sealing layer fills an upper portion of the opening.

Vacuum channel transistor structures with sub-10 nanometer nanogaps and layered metal electrodes

A technique relates to a semiconductor device. An emitter electrode and a collector electrode are formed in a dielectric layer such that a nanogap separates the emitter electrode and the collector electrode, a portion of the emitter electrode including layers. A channel is formed in the dielectric layer so as to traverse the nanogap. A top layer is formed over the channel so as to cover the channel and the nanogap without filling in the channel and the nanogap, thereby forming a vacuum channel transistor structure.

PRINTED ACTIVE DEVICE
20170345610 · 2017-11-30 ·

A method of manufacturing an article with integral active electronic component comprising: using an additive manufacturing process to: a) form a non-electrically conductive substrate; b) form a non-electrically conductive perforated layer having an aperture; c) form electrically conductive anode and cathode elements spaced in the aperture; d) deposit a conductive electrical connection to each of the elements suitable for imparting an electrical potential difference between the elements; e) form a non-electrically conductive sealing layer atop the perforated layer so as to retain and seal the aperture in the perforated layer.

PRINTED ACTIVE DEVICE
20170345610 · 2017-11-30 ·

A method of manufacturing an article with integral active electronic component comprising: using an additive manufacturing process to: a) form a non-electrically conductive substrate; b) form a non-electrically conductive perforated layer having an aperture; c) form electrically conductive anode and cathode elements spaced in the aperture; d) deposit a conductive electrical connection to each of the elements suitable for imparting an electrical potential difference between the elements; e) form a non-electrically conductive sealing layer atop the perforated layer so as to retain and seal the aperture in the perforated layer.

Emitter with deep structuring on front and rear surfaces
09824843 · 2017-11-21 · ·

An emitter has a basic unit with at least one emission surface. Accordingly, the basic unit has deep structuring in a region of the at least one emission surface. More specifically, the basic unit has the deep structuring on both a front side and on a rear side in the region of the emission surface for improving emission properties.

VACUUM TUBE FOR AMPLIFIER CIRCUIT, AND AMPLIFIER CIRCUIT USING SAME

A vacuum tube for amplifier circuit includes: a light incidence window that transmits signal light; a photoelectric conversion unit that converts the signal light transmitted through the light incidence window into photoelectrons; an output unit that has an anode, on which the photoelectrons are incident, and outputs a signal corresponding to the incident photoelectrons; and a grid electrode that is disposed in a path of the photoelectrons from the photoelectric conversion unit to the anode and controls the amount of photoelectrons incident on the anode.

Device for controlling electron flow and method for manufacturing said device

A device for controlling electron flow is provided. The device comprises a cathode, an elongate electrical conductor embedded in a diamond substrate, an anode, and a control electrode provided on the substrate surface for modifying the electric field in the region of the end of the conductor. A method of manufacturing the device is also provided.

GATE ALL AROUND VACUUM CHANNEL TRANSISTOR
20210273116 · 2021-09-02 · ·

A vacuum channel transistor having a vertical gate-all-around (GAA) architecture provides high performance for high-frequency applications, and features a small footprint compared with existing planar devices. The GAA vacuum channel transistor features stacked, tapered source and drain regions that are formed by notching a doped silicon pillar using a lateral oxidation process. A temporary support structure is provided for the pillar during formation of the vacuum channel. Performance of the GAA vacuum channel transistor can be tuned by replacing air in the channel with other gases such as helium, neon, or argon. A threshold voltage of the GAA vacuum channel transistor can be adjusted by altering dopant concentrations of the silicon pillar from which the source and drain regions are formed.