An additively manufactured apparatus having a gas filled sealed cavity containing at least two additively manufactured cathodes and an additively manufactured anode spaced from the cathodes such that a continuous electric discharge of the gas stimulated between at least one of the cathodes and the anode provides a Boolean function output at the anode corresponding to electrical input signals at two of the cathodes.

An additively manufactured apparatus having a gas filled sealed cavity containing at least two additively manufactured cathodes and an additively manufactured anode spaced from the cathodes such that a continuous electric discharge of the gas stimulated between at least one of the cathodes and the anode provides a Boolean function output at the anode corresponding to electrical input signals at two of the cathodes.

A vacuum tube for amplifier circuit includes: a light incidence window that transmits signal light; a photoelectric conversion unit that converts the signal light transmitted through the light incidence window into photoelectrons; an output unit that has an anode, on which the photoelectrons are incident, and outputs a signal corresponding to the incident photoelectrons; and a grid electrode that is disposed in a path of the photoelectrons from the photoelectric conversion unit to the anode and controls the amount of photoelectrons incident on the anode.

A substrate processing apparatus, for generating a plasma from a gas by a high frequency energy and etching a substrate in a processing chamber by radicals in the plasma, includes a high frequency power supply configured to supply the high frequency energy into the processing chamber, a gas supply source configured to introduce the gas into the processing chamber, a mounting table configured to mount the substrate thereon, and a partition plate provided in the processing chamber and configured to divide an inner space of the processing chamber into a plasma generation space and a substrate processing space and suppress passage of ions therethrough. The partition plate and a portion of an inner wall surface of the processing chamber which is positioned at least above the mounting table are covered by a dielectric material having a recombination coefficient of 0.002 or less.

A field emitter array (FEA) vacuum transistor is disclosed which includes a substrate and a plurality of nanorods formed of a first polarity dopant on the substrate, wherein the dopant density is between about 10.sup.13 cm.sup.−3 to about 10.sup.15 cm.sup.−3.

A field emitter array (FEA) vacuum transistor is disclosed which includes a substrate and a plurality of nanorods formed of a first polarity dopant on the substrate, wherein the dopant density is between about 10.sup.13 cm.sup.−3 to about 10.sup.15 cm.sup.−3.

A field emitter array (FEA) vacuum transistor is disclosed which includes a substrate and a plurality of nanorods formed of a first polarity dopant on the substrate, wherein the dopant density is between about 10.sup.13 cm.sup.−3 to about 10.sup.15 cm.sup.−3.

A field emitter array (FEA) vacuum transistor is disclosed which includes a substrate and a plurality of nanorods formed of a first polarity dopant on the substrate, wherein the dopant density is between about 10.sup.13 cm.sup.−3 to about 10.sup.15 cm.sup.−3.

A horizontal vacuum channel transistor is provided. The horizontal transistor includes a substrate, horizontal emitter and collector electrodes formed in a layer of semiconductor material of the substrate, and a horizontal insulated gate located between the emitter and collector electrodes. The emitter electrode includes multiple horizontally-aligned emitter tips connected to a planar common portion, and the collector electrode includes a planar portion. The gate includes multiple horizontally-aligned gate apertures passing through the gate that each correspond to one of the emitter tips of the emitter electrode. The minimum distance between the emitter and collector electrodes is less than about 180 nm. Also provided are a vertical vacuum channel transistor having vertically-stacked emitter and collector electrodes, and methods for fabricating vacuum channel transistors.

A field emitter array (FEA) vacuum transistor is disclosed which includes a substrate and a plurality of nanorods formed of a first polarity dopant on the substrate.