An electron source (2) for generating an electron beam (8) having a cathode (1) and an anode (4) in the form of a graphene layer (6, 12) epitaxially grown on a silicon carbide substrate (5). The invention is suitable for monolithic preparation of a miniaturized source of a high-energy focused electron beam, including its use as an on-chip X-ray source. All components can be prepared from or on a single silicon carbide chip.

A technique relates to a semiconductor device. An emitter electrode and a collector electrode are formed in a dielectric layer such that a nanogap separates the emitter electrode and the collector electrode, a portion of the emitter electrode including layers. A channel is formed in the dielectric layer so as to traverse the nanogap. A top layer is formed over the channel so as to cover the channel and the nanogap without filling in the channel and the nanogap, thereby forming a vacuum channel transistor structure.

A technique relates to a semiconductor device. An emitter electrode and a collector electrode are formed in a dielectric layer such that a nanogap separates the emitter electrode and the collector electrode, a portion of the emitter electrode including layers. A channel is formed in the dielectric layer so as to traverse the nanogap. A top layer is formed over the channel so as to cover the channel and the nanogap without filling in the channel and the nanogap, thereby forming a vacuum channel transistor structure.

A technique relates to a semiconductor device. An emitter electrode and a collector electrode are formed in a dielectric layer such that a nanogap separates the emitter electrode and the collector electrode, a portion of the emitter electrode including layers. A channel is formed in the dielectric layer so as to traverse the nanogap. A top layer is formed over the channel so as to cover the channel and the nanogap without filling in the channel and the nanogap, thereby forming a vacuum channel transistor structure.

A technique relates to a semiconductor device. An emitter electrode and a collector electrode are formed in a dielectric layer such that a nanogap separates the emitter electrode and the collector electrode, a portion of the emitter electrode including layers. A channel is formed in the dielectric layer so as to traverse the nanogap. A top layer is formed over the channel so as to cover the channel and the nanogap without filling in the channel and the nanogap, thereby forming a vacuum channel transistor structure.

A method for fabricating silicon die stacks for electron emitter chips by applying sintering to bind a silicon substrate die to other die layers. Metal powder is applied to the bonding surface of the die, covered with the chip carrier or chip and compressed between two heated plates. The bonding pads of the die may be conductively coupled to corresponding bonding pads of the other die layers.

A chip mounted field emitter array method for their fabrication by applying sintering to bind a substrate die to other die layers. Metal powder is applied to the bonding surface of the die, covered with the chip carrier or chip and compressed between two heated plates. The bonding pads of the die may be conductively coupled to corresponding bonding pads of the other die layers.

A backend field emission device may include a field emission device in a backend of line (BEOL) layer, such as an interconnect layer. In one example, a backend field emission device includes a first electrode coupled with a first conductive interconnect, a second electrode coupled with a second conductive interconnect, an airgap between the first electrode and the second electrode, and a third electrode between the first electrode and the second electrode and coplanar with the airgap.