A semiconductor device includes a first standard cell disposed on a substrate in a first row and having a first cell height; a second standard cell disposed on the substrate in a second row, adjacent to the first row, second standard cell having a second cell height, different from the first cell height; and a power line extending in a first direction along a boundary between the first standard cell and the second standard cell.

A semiconductor device includes a substrate having cell areas and power areas that are alternately arranged in a second direction. Gate structures extend in the second direction. The gate structures are spaced apart from each other in a first direction perpendicular to the second direction. Junction layers are arranged at both sides of each gate structure. The junction layers are arranged in the second direction such that each of the junction layer has a flat portion that is proximate to the power area. Cutting patterns are arranged in the power areas. The cutting patterns extend in the first direction such that each of the gate structures and each of the junction layers in neighboring cell areas are separated from each other by the cutting pattern.

Semiconductor structures are provided. Each transistor includes a first source/drain region over a semiconductor fin, a second source/drain region over the semiconductor fin, a channel region in the semiconductor fin and between the first and second source/drain regions, and a metal gate electrode formed on the channel region and extending in a second direction. In a first transistor of the transistors, the first source/drain region is formed between the metal gate electrode of the first transistor and the metal gate electrode of a second transistor of the transistors. The second source/drain region is formed between the metal gate electrode of the first transistor and the dielectric-base dummy gate. A first contact of the first source/drain region is separated from a spacer of the metal gate electrode of the first transistor. A second contact of the second source/drain region is in contact with a spacer of the dielectric-base dummy gate.

A semiconductor integrated circuit device includes a first power wiring that is formed on a semiconductor substrate and that extends in a first direction, a second power wiring that extends in the first direction such that the second power wiring is separated from the first power wiring, a first diffusion layer that is used for a p-channel type MOSFET and that is formed in a region between the first power wiring and the second power wiring, a second diffusion layer that is used for an n-channel type MOSFET and that is formed on a side of the second power wiring with respect to the first diffusion layer in the region between the first power wiring and the second power wiring, a first gate electrode that extends in a second direction perpendicular to the first direction and that straddles the first diffusion layer, a second gate electrode that extends in the second direction and that straddles the second diffusion layer, and a third diffusion layer for backgates that is formed below at least one of the first power wiring and the second power wiring and that is placed in a dotted manner along the first direction.

A semiconductor device includes a substrate having cell areas and power areas that are alternately arranged in a second direction. Gate structures extend in the second direction. The gate structures are spaced apart from each other in a first direction perpendicular to the second direction. Junction layers are arranged at both sides of each gate structure. The junction layers are arranged in the second direction such that each of the junction layer has a flat portion that is proximate to the power area. Cutting patterns are arranged in the power areas. The cutting patterns extend in the first direction such that each of the gate structures and each of the junction layers in neighboring cell areas are separated from each other by the cutting pattern.

Provided is an integrated circuit (IC) device including a logic cell having an area defined by a cell boundary. The logic cell includes a first device region, a device isolation region, and a second device region. The first device region and the second device region are arranged apart from each other in a first direction that is perpendicular to a second direction. The device isolation region is between the first device region and the second device region. A first maximum length of the first device region in the second direction is less than a width of the cell boundary in the second direction, and a second maximum length of the second device region is substantially equal to the width of the cell boundary in the second direction.

A semiconductor device is provided. The semiconductor device includes a substrate including an active pattern, a gate electrode extending in a first direction and crossing the active pattern which extends in a second direction, a separation structure crossing the active pattern and extending in the first direction, a first gate dielectric pattern disposed on a side surface of the gate electrode, a second gate dielectric pattern disposed on a side surface of the separation structure, and a gate capping pattern covering a top surface of the gate electrode. A level of a top surface of the separation structure is higher than a level of a top surface of the gate capping pattern.

A local interconnect is formed in contact with an upper surface of an impurity diffusion region and extends to below a potential supply interconnect. A contact hole electrically couples the local interconnect to the potential supply interconnect. The local interconnect, which is formed in contact with the upper surface of the impurity diffusion region, is used for electrically coupling the impurity diffusion region to the potential supply interconnect.

A semiconductor structure is provided. A logic cell includes a first transistor in a first active region, a second gate electrode and a third gate electrode on opposite sides of the first transistor, a second transistor in a second active region, and a first isolation structure and a second isolation structure on opposite edges of the second active region. The first transistor includes a first gate electrode extending in a first direction. The second and third gate electrodes extend in the first direction, and the first and second isolation structures extend in the first direction. The second transistor and the first transistor share the first gate electrode. The first isolation structure is aligned with the second gate structure in the first direction, and the second isolation structure is aligned with the third gate structure in the first direction.

A semiconductor device includes a first standard cell disposed on a substrate in a first row and having a first cell height; a second standard cell disposed on the substrate in a second row, adjacent to the first row, second standard cell having a second cell height, different from the first cell height; and a power line extending in a first direction along a boundary between the first standard cell and the second standard cell.