A method for etching a main surface of a thin layer of a substrate, which comprises immersing the substrate n an etching bath so as to expose the main surface to an etching agent, the substrate being oriented relative to the bath such that: —when it is introduced into the bath, the main surface is gradually immersed from an initial introduction point (PII) to an end introduction point (PFI), at an introduction speed, and —when it exits the bath, the main surface gradually emerges from an initial exit point (PIS) to an end exit point (PFS), at an exit speed, the method being characterized in that: —the introduction speed is chosen in such a way as to etch the main surface according to a first non-uniform profile between the initial introduction point (PII) and the end introduction point (PFI), and/or —the exit speed is chosen in such a way as to etch the main surface according to a second non-uniform profile between the initial exit point (PIS) and the end exit point (PFS), in order to compensate for non-uniformities in the thickness of the thin layer.

Methods and apparatus for increasing a bonded area between an ultrathin die and a substrate. In some embodiments, the method may include cleaning the die and the substrate, placing the die on an upper surface of the substrate, compacting the die to the substrate using a downward force of at least one compacting roller on the die and the upper surface of the substrate to increase a bonded area between the die and the upper surface of the substrate, and annealing the die and the substrate. The compacting roller has a soft surface layer that engages with the die and the upper surface of the substrate. The soft surface layer has a Shore hardness of greater than approximately 30 and less than approximately 80. In some embodiments, the substrate and/or the compacting roller may rotate during contact with each other.

Methods of doping a semiconductor material are disclosed. Some embodiments provide for conformal doping of three dimensional structures. Some embodiments provide for doping with high concentrations of boron for p-type doping.

A substrate processing method includes: holding a substrate having a processing target surface and an opposite surface which is opposite to the processing target surface; preheating a center portion of the opposite surface of the substrate; after the preheating, ejecting a sulfuric acid hydrogen peroxide mixture (SPM) to a peripheral edge portion of the processing target surface of the substrate; and after the ejecting, moving an ejection position of the SPM from the peripheral edge portion of the processing target surface to a center portion of the substrate.

There is provided a method of cleaning a substrate processing apparatus in which a drying process of drying a substrate whose surface is wet with a liquid is performed by bring the substrate into contact with a supercritical fluid, the method including: diffusing a first cleaning fluid in an interior of the substrate processing apparatus, the first cleaning fluid being obtained by mixing the supercritical fluid with a solvent containing polar molecules and having a lower boiling point than a boiling point of the liquid; and discharging the first cleaning fluid from the interior of the substrate processing apparatus, that occurs after the diffusing the first cleaning fluid.

A method for manufacturing a semiconductor element of the present disclosure includes: a step of preparing a substrate; a first element forming step of forming a first semiconductor layer in a first region on a surface of the substrate; a first element separating step of separating the first semiconductor layer from the substrate; and a second element forming step of forming a second semiconductor layer in a second region on the surface of the substrate from which the first semiconductor layer is separated. Additionally, in the method for manufacturing a semiconductor element of the present disclosure, at least a portion of the second region overlaps the first region.

The method that includes the step of a cleaning a surface of a silicon wafer and forming a sacrificial layer on top of the silicon wafer. The wafer undergoes further processing, wherein the processing includes forming at least one layer directly on top of the sacrificial layer. Immediately prior to the insertion into a dilute refrigeration unit removing a portion of the sacrificial layer by exposing the portion of the sacrificial layer to a solvent.

An apparatus for semiconductor manufacturing includes an input port to receive a carrier, wherein the carrier includes a carrier body, a housing installed onto the carrier body, and a filter installed between the carrier body and the housing. The apparatus further includes a first robotic arm to uninstall the housing from the carrier and to reinstall the housing into the carrier; one or more second robotic arms to remove the filter from the carrier and to install a new filter into the carrier; and an output port to release the carrier to production.

A method includes bonding a front side surface of a first wafer to a second wafer; performing a multi-trimming process on the first and second wafers from a back side surface of the first wafer, the multi-trimming process comprising: performing a first trimming step from the back side surface of the first wafer to cut through a periphery of the first wafer; performing a second trimming step on the second wafer to partially cut a periphery of the second wafer to form a first step-like structure; and performing a third trimming step on the second wafer to partially cut the periphery of the second wafer to form a second step-like structure connecting down from the first step-like structure; after performing the multi-trimming process, forming a coating material at least over the periphery of the second wafer.

A system includes a plurality of semiconductor processing tools; a carrier purge station; a carrier repair station; and an overhead transport (OHT) loop for transporting one or more substrate carriers among the plurality of semiconductor processing tools, the carrier purge station, and the carrier repair station. The carrier purge station is configured to receive a substrate carrier from one of the plurality of semiconductor processing tools, purge the substrate carrier with an inert gas, and determine if the substrate carrier needs repair. The carrier repair station is configured to receive a substrate carrier to be repaired and replace one or more parts in the substrate carrier.