An etching method and a plasma processing apparatus form a recess with an intended shape. The etching method includes (a) providing a substrate, the substrate including a silicon-containing film and a mask on the silicon-containing film; (b) etching the silicon-containing film with a first plasma to form a recess, the first plasma generated from a first process gas; (c) supplying a second plasma to the substrate, the second plasma generated from a second process gas comprising tungsten; and (d) etching the recess with a third plasma generated from a third process gas.

A method for making a semiconductor device includes patterning at least one dielectric layer disposed over a conductive cap layer to form a via opening penetrating through the at least one dielectric layer to expose the conductive cap layer and to form a top portion of the conductive cap layer into a metal oxide layer; converting the metal oxide layer to a metal oxynitride layer by a soft ashing process using a processing gas containing nitrogen gas; removing the metal oxynitride layer from a remaining portion of the conductive cap layer; and forming a via contact in the via opening to electrically connect the remaining portion of the conductive cap layer.

A semiconductor structure includes a multilayer structure having a first layer and a second layer disposed on the first layer. The semiconductor structure further includes at least a first via extending from a top of the second layer to a top of a first metal contact disposed in the first layer. A polymer film is disposed on at least a portion of sidewalls of the first via.

A method includes forming a dielectric layer over an epitaxial source/drain region. An opening is formed in the dielectric layer. The opening exposes a portion of the epitaxial source/drain region. A barrier layer is formed on a sidewall and a bottom of the opening. An oxidation process is performing on the sidewall and the bottom of the opening. The oxidation process transforms a portion of the barrier layer into an oxidized barrier layer and transforms a portion of the dielectric layer adjacent to the oxidized barrier layer into a liner layer. The oxidized barrier layer is removed. The opening is filled with a conductive material in a bottom-up manner. The conductive material is in physical contact with the liner layer.

A method for manufacturing a semiconductor device includes: forming an isolating layer on a surface of a substrate; forming a groove on the isolating layer, where the groove penetrates the isolating layer; forming a protection layer in the groove and on the isolating layer; forming a dielectric layer on the protection layer; and forming a contact hole, where the contact hole penetrates the protection layer and the dielectric layer to the surface of the substrate, respectively. The method for manufacturing the semiconductor device according to the present invention can be used not only in chemical vapor deposition but also in a process of a metal wire of a short-circuit in physical vapor deposition.

Provided are a cleaning agent and a preparation method and the use thereof. The cleaning agent is prepared from the following raw materials comprising the following mass fraction of components: 0.5%-20% of an oxidant containing iodine, 0.5%-20% of an etchant containing boron, 1%-50% of a pyrrolidinone solvent, 1%-20% of a corrosion inhibitor, 0.01%-5% of a metal ion-free surfactant, and water, with the sum of the mass fraction of each component being 100%, the pH of the cleaning agent is 7.5-13.5, and the corrosion inhibitor is one or more of a benzotriazole corrosion inhibitor, a hydrazone corrosion inhibitor, a carbazone corrosion inhibitor and a thiocarbohydrazone corrosion inhibitor. The cleaning agent can efficiently remove nitrides from hard mask residues with little effects on metals and low-κ dielectric materials, and has a good selectivity.

An object of the present invention is to provide a treatment liquid for a semiconductor device, which is excellent in removal performance for residues present on a substrate, and to provide a substrate washing method using the treatment liquid.

The treatment liquid of the present invention is a treatment liquid for a semiconductor device, which includes water, a basic compound, hexylene glycol, and a compound A that is at least one kind selected from the group consisting of isobutene, (E)-2-methyl-1,3-pentadiene, 4-methyl-1,3-pentadiene, 2,2,4-trimethyloxetane, 4-methyl-3-penten-2-ol, and 2,4,4,6-tetramethyl-1,3-dioxane.

A device includes an isolation structure, a source/drain epi-layer, a contact, a first dielectric layer, and a second dielectric layer. The isolation structure is embedded in a substrate. The source/drain epi-layer is embedded in the substrate and is in contact with the isolation structure. The contact is over the source/drain epi-layer. The first dielectric layer wraps the contact. The second dielectric layer is between the contact and the first dielectric layer. The first and second dielectric layers include different materials, and a portion of the source/drain epi-layer is directly between a bottom portion of the second dielectric layer and a top portion of the isolation structure.

Methods for forming interconnects on a substrate with low resistivity and high dopant interfaces. In some embodiments, a method includes depositing a first copper layer with a dopant with a first dopant content of 0.5 percent to 10 percent in the interconnect by sputtering a first copper-based target at a first temperature of zero degrees Celsius to 200 degrees Celsius, annealing the substrate at a second temperature of 200 degrees Celsius to 400 degrees Celsius to reflow the first copper layer, depositing a second copper layer with the dopant with a second dopant content of zero percent to 0.5 percent by sputtering a second copper-based target at the first temperature of zero degrees Celsius to 200 degrees Celsius, and annealing the substrate at a third temperature of 200 degrees Celsius to 400 degrees Celsius to reflow the second copper layer.

A MOSFET includes a semiconductor body having a first side, a drift region, a body region forming a first pn-junction with the drift region, a source region forming a second pn-junction with the body region, in a vertical cross-section, a dielectric structure on the first side and having an upper side; a first gate electrode, a second gate electrode, a contact trench between the first and second gate electrodes, extending through the dielectric structure to the source region, in a horizontal direction a width of the contact trench has, in a first plane, a first value, and, in a second plane, a second value which is at most about 2.5 times the first value, and a first contact structure arranged on the dielectric structure having a through contact portion arranged in the contact trench, and in Ohmic contact with the source region.