A device includes a plurality of fin structures that each protrude vertically upwards out of a substrate and each extend in a first direction in a top view. A gate structure is disposed over the fin structures. The gate structure extends in a second direction in the top view. The second direction is different from the first direction. The fin structures have a fin pitch equal to a sum of: a dimension of one of the fin structures in the second direction and a distance between an adjacent pair of the fin structures in the second direction. An end segment of the gate structure extends beyond an edge of a closest one of the fin structures in the second direction. The end segment has a tapered profile in the top view or is at least 4 times as long as the fin pitch in the second direction.

A method of forming a semiconductor device includes depositing a film over a dielectric layer. The dielectric layer is over a first fin, a second fin, and within a trench between the first fin and the second fin. The method further includes etching top portions of the film, performing a treatment on the dielectric layer to remove impurities after etching the top portions of the film, and filling the trench over the remaining portions of the film. The treatment includes bombarding the dielectric layer with radicals.

A substrate processing apparatus includes a processing chamber; a susceptor provided in the processing chamber, wherein the susceptor is configured to support a substrate; a first plasma generator disposed on one side of the processing chamber; and a second plasma generator disposed on another side of the processing chamber, wherein the second plasma generator is configured to generate plasma by simultaneously supplying a sinusoidal wave signal and a non-sinusoidal wave signal to the susceptor. By using a substrate processing apparatus, a signal source device, and a method of processing a material layer according to the inventive concept, a smooth etched surface may be obtained for a crystalline material layer without a risk of device damage by RDC.

Methods are presented for forming multi-threshold field effect transistors. The methods generally include depositing and patterning an organic planarizing layer to protect underlying structures formed in a selected one of the nFET region and the pFET region of a semiconductor wafer. In the other one of the nFET region and the pFET region, structures are processed to form an undercut in the organic planarizing layer. The organic planarizing layer is subjected to a reflow process to fill the undercut. The methods are effective to protect a boundary between the nFET region and the pFET region.

The present disclosure provides a method of manufacturing a semiconductor structure and a semiconductor device etching equipment. The semiconductor structure manufacturing method includes: providing a semiconductor structure to be processed, putting the semiconductor structure to be processed in a processing chamber, wherein the semiconductor structure to be processed includes a substrate and target structures to be processed located on the substrate, and sidewalls of the target structures to be processed are covered with bromine-containing polymer layers; removing the bromine-containing polymer layers, and forming a semiconductor structure; and removing products resulting from a process of removing the bromine-containing polymer layers from the processing chamber.

A semiconductor structure formed by the method for forming the semiconductor structure includes: a substrate, on which an insulating layer is formed; metal conductive layers located on the insulating layer; and an isolation structure located between two adjacent ones of the metal conductive layers.

In an embodiment, a method includes: receiving, within a processing chamber, a wafer with a photoresist mask above a metal layer, wherein the processing chamber is connected to a gas source; applying an etchant configured to etch the metal layer in accordance with the photoresist mask within the processing chamber; and applying gas from the gas source to perform plasma ashing in the processing chamber.

A method of processing a substrate that includes: loading the substrate in a processing system, the substrate including a metal having a metal surface and a first dielectric material having a dielectric material surface, the metal surface and the dielectric material surface being at the same level; etching the metal to form a recessed metal surface below the dielectric material surface; selectively forming a self-assembled monolayer (SAM) on the recessed metal surface using a spin-on process; and depositing a dielectric film including a second dielectric material on the dielectric material surface.

Provided are a cleaning agent and a preparation method and the use thereof. The cleaning agent is prepared from the following raw materials comprising the following mass fraction of components: 0.5%-20% of an oxidant containing iodine, 0.5%-20% of an etchant containing boron, 1%-50% of a pyrrolidinone solvent, 1%-20% of a corrosion inhibitor, 0.01%-5% of a metal ion-free surfactant, and water, with the sum of the mass fraction of each component being 100%, the pH of the cleaning agent is 7.5-13.5, and the corrosion inhibitor is one or more of a benzotriazole corrosion inhibitor, a hydrazone corrosion inhibitor, a carbazone corrosion inhibitor and a thiocarbohydrazone corrosion inhibitor. The cleaning agent can efficiently remove nitrides from hard mask residues with little effects on metals and low-κ dielectric materials, and has a good selectivity.

A semiconductor device includes a gate electrode, a source/drain structure, a lower contact contacting either of the gate electrode or the source/drain structure, and an upper contact disposed in an opening formed in an interlayer dielectric (ILD) layer and in direct contact with the lower contact. The upper contact is in direct contact with the ILD layer without an interposing conductive barrier layer, and the upper contact includes ruthenium.