Patent classifications
H01L21/02112
Gate spacer structure and method of forming same
A semiconductor device and a method of forming the same are provided. The method includes forming a sacrificial gate structure over an active region. A first spacer layer is formed along sidewalls and a top surface of the sacrificial gate structure. A first protection layer is formed over the first spacer layer. A second spacer layer is formed over the first protection layer. A third spacer layer is formed over the second spacer layer. The sacrificial gate structure is replaced with a replacement gate structure. The second spacer layer is removed to form an air gap between the first protection layer and the third spacer layer.
MANUFACTURING METHOD OF ITO THIN FILM BASED ON SOLUTION METHOD
A manufacturing method of an indium tin oxide (ITO) thin film based on a solution method is disclosed. The manufacturing method includes: a step of providing an array substrate; a step of obtaining a dispersion solution by mixing ITO grains, an organic small molecule phase transfer agent, and an N-chlorosuccinimide (NCs) solution; a step of obtaining uniformly assembled ITO grains by coating the dispersion solution onto a passivation layer and baking to remove the organic small molecule phase transfer agent; and a step of obtaining the ITO thin film by annealing at an inert atmosphere to refine the ITO grains.
Semiconductor device and manufacturing method thereof
A fin field effect transistor (Fin FET) device includes a fin structure extending in a first direction and protruding from an isolation insulating layer disposed over a substrate. The fin structure includes a well layer, an oxide layer disposed over the well layer and a channel layer disposed over the oxide layer. The Fin FET device includes a gate structure covering a portion of the fin structure and extending in a second direction perpendicular to the first direction. The Fin FET device includes a source and a drain. Each of the source and drain includes a stressor layer disposed in recessed portions formed in the fin structure. The stressor layer extends above the recessed portions and applies a stress to a channel layer of the fin structure under the gate structure. The Fin FET device includes a dielectric layer formed in contact with the oxide layer and the stressor layer in the recessed portions.
METAL-DOPED BORON FILMS
Exemplary deposition methods may include delivering a boron-containing precursor to a processing region of a semiconductor processing chamber. The methods may include delivering a dopant-containing precursor with the boron-containing precursor. The dopant-containing precursor may include a metal. The methods may include forming a plasma of all precursors within the processing region of the semiconductor processing chamber. The methods may include depositing a doped-boron material on a substrate disposed within the processing region of the semiconductor processing chamber. The doped-boron material may include greater than or about 80 at. % of boron in the doped-boron material.
SEMICONDUCTOR DEVICES
Disclosed are a semiconductor device and a method of fabricating the same. The semiconductor device may include a substrate having a groove therein extending in a first direction, a gate insulating layer in the groove, a first conductive pattern in the groove and on the gate insulating layer, and a word line capping pattern in the groove and on the first conductive pattern. The first conductive pattern may include a first material and may include a first conductive portion adjacent to the word line capping pattern and a second conductive portion adjacent to a bottom end of the groove. A largest dimension of a grain of the first material of the first conductive portion may be equal to or larger than that of the first material of the second conductive portion.
Semiconductor device and method for manufacturing the same
A semiconductor device is manufactured using a transistor in which an oxide semiconductor is included in a channel region and variation in electric characteristics due to a short-channel effect is less likely to be caused. The semiconductor device includes an oxide semiconductor film having a pair of oxynitride semiconductor regions including nitrogen and an oxide semiconductor region sandwiched between the pair of oxynitride semiconductor regions, a gate insulating film, and a gate electrode provided over the oxide semiconductor region with the gate insulating film positioned therebetween. Here, the pair of oxynitride semiconductor regions serves as a source region and a drain region of the transistor, and the oxide semiconductor region serves as the channel region of the transistor.
HIGH MODULUS BORON-BASED CERAMICS FOR SEMICONDUCTOR APPLICATIONS
Various embodiments herein relate to methods, apparatus, and systems for depositing a boron-based ceramic film on a substrate. Advantageously, the boron-based ceramic films described herein can be formed at relatively low temperatures (e.g., about 600C or less), while still achieving very high quality materials that exhibit good mechanical strength (e.g., high hardness and Young's modulus), good etch selectivity, amorphous morphology, etc. The films herein also have low hydrogen content, low oxygen content, and low halide content. In many cases, the films may be formed through a reaction between a boron halide and a saturated or unsaturated hydrocarbon, in the presence of plasma.
HALOGENATION-BASED GAPFILL METHOD AND SYSTEM
A method and system for forming material within a gap on a surface of a substrate are disclosed. An exemplary method includes forming a material layer on a surface of the substrate within a first reaction chamber, exposing the material layer to a halogen reactant in a second reaction chamber to thereby form a flowable layer comprising a halogen within the gap, and optionally exposing the flowable layer to a converting reactant in a third reaction chamber to form a converted material within the gap. Exemplary methods can further include a step of heat treating the flowable layer or the converted material. Exemplary systems can perform the method.
Semiconductor structure and planarization method thereof
A planarization method includes forming a dielectric layer over a polish stop layer. The dielectric layer is polished until reaching the polish stop layer, and the polished dielectric layer has a concave top surface. A compensation layer is formed over the concave top surface. The compensation layer is polished.
Method for preparing semiconductor device structure with fine boron nitride spacer patterns
The present disclosure provides a method for preparing a semiconductor device structure with fine boron nitride spacer patterns. The method includes undercutting a photoresist pattern over a semiconductor substrate, and forming an inner spacer element over a sidewall surface of the photoresist pattern. The inner spacer element has a portion extending into a recess (i.e., the undercut region) of the photoresist pattern to form a footing, and a width of the portion of the inner spacer element increases continuously as the portion extends toward the semiconductor substrate. As a result, the inner spacer element may be prevented from collapsing after removal of the photoresist pattern.