A method of manufacturing a semiconductor device includes forming a three-dimensional (3D) structure on a substrate, forming an adsorption control layer to cover an upper portion of the 3D structure, and forming a material layer on the adsorption control layer and on a lower portion of the 3D structure that is not covered by the adsorption control layer, wherein a minimum thickness of the material layer on the adsorption control layer is less than a maximum thickness of the material layer on the lower portion of the 3D structure.

A method of manufacturing a semiconductor device includes forming a three-dimensional (3D) structure on a substrate, forming an adsorption control layer to cover an upper portion of the 3D structure, and forming a material layer on the adsorption control layer and on a lower portion of the 3D structure that is not covered by the adsorption control layer, wherein a minimum thickness of the material layer on the adsorption control layer is less than a maximum thickness of the material layer on the lower portion of the 3D structure.

A manufacturing method for a light emitting device, a light emitting device, and a hybrid light emitting device, the manufacturing method comprises the following steps: step S1: disposing a mask plate having a plurality of hollow portions on a substrate; step S2: applying, by using a solution method, ink on a surface of the substrate by using the hollow portions; and step S3: drying or solidifying the ink on the surface of the substrate to form a light emitting layer or a functional layer.

A method for forming a semiconductor device involves selecting a substrate on which a wurtzite III-nitride alloy layer will be formed, and a piezoelectric polarization and an effective piezoelectric coefficient for the wurtzite III-nitride alloy layer. It is determined whether there is a wurtzite III-nitride alloy composition satisfying the selected effective piezoelectric coefficient. It is also determined whether there is a thickness for a layer formed from the wurtzite III-nitride alloy composition satisfying the selected piezoelectric polarization based on the selected substrate and the selected effective piezoelectric coefficient. Responsive to the determination that there is a wurtzite III-nitride alloy composition having a lattice constant satisfying the selected effective piezoelectric coefficient and a thickness for the layer formed from the wurtzite III-nitride alloy composition satisfying the selected piezoelectric polarization, the wurtzite III-nitride alloy layer is formed on the substrate having the wurtzite III-nitride alloy composition satisfying the selected effective piezoelectric coefficient and having the thickness satisfying the selected piezoelectric polarization.

A material layer having recesses is formed on a substrate including a high pattern density area and a low pattern density area. A first dielectric layer and a second dielectric layer are sequentially formed to cover the material layer, wherein a top surface of the first dielectric layer in the high pattern density area is higher than a top surface of the first dielectric layer in the low pattern density area, thereby a thickness of the second dielectric layer in the low pattern density area being thicker than a thickness of the second dielectric layer in the high pattern density area. An etching back process is performed to remove the second dielectric layer and the first dielectric layer, wherein the etching rate of the etching back process to the second dielectric layer is lower than the etching rate of the etching back process to the first dielectric layer.

A material layer having recesses is formed on a substrate including a high pattern density area and a low pattern density area. A first dielectric layer and a second dielectric layer are sequentially formed to cover the material layer, wherein a top surface of the first dielectric layer in the high pattern density area is higher than a top surface of the first dielectric layer in the low pattern density area, thereby a thickness of the second dielectric layer in the low pattern density area being thicker than a thickness of the second dielectric layer in the high pattern density area. An etching back process is performed to remove the second dielectric layer and the first dielectric layer, wherein the etching rate of the etching back process to the second dielectric layer is lower than the etching rate of the etching back process to the first dielectric layer.

[Object] Provided are a laminate film and an electrode substrate film with excellent etching quality, in which a circuit pattern formed by etching processing is less visible under highly bright illumination, and a method of manufacturing the same. [Solving Means] A laminate film includes a transparent substrate 60 formed of a resin film and a layered film provided on at least one surface of the transparent substrate. The layered film includes metal absorption layers 61 and 63 as a first layer and metal layers (62, 65), (64, 66) as a second layer, counted from the transparent substrate side. The metal absorption layers are formed by a reactive sputtering method which uses a metal target made of Ni alone or an alloy containing two or more elements selected from Ni, Ti, Al, V, W, Ta, Si, Cr, Ag, Mo, and Cu, and a reactive gas containing oxygen. The reactive gas contains hydrogen.

A method of forming a silicon-germanium heterojunction bipolar transistor (hbt) device is provided. The method includes forming a stack of four doped semiconductor layers on a semiconductor substrate. The method further includes forming a dummy emitter contact and contact spacers on a fourth doped semiconductor layer of the stack of four doped semiconductor layers, and removing portions of the second, third, and fourth semiconductor layers to form a vertical fin. The method further includes recessing the second and fourth doped semiconductor layers, and depositing a condensation layer on the second, third, and fourth doped semiconductor layers. The method further includes reacting the condensation layer with the third doped semiconductor layer to form a protective segment on a condensed protruding portion.

The present disclosure relates to a method of preparing a monomolecular nano-thin film, including: coating, on a substrate, a dispersion solution containing a compound represented by the following Chemical Formula 1; and performing annealing to the coated substrate:

##STR00001## in the above Chemical Formula 1, X and Y are each independently nitrogen, carbon, sulfur, or oxygen, R.sub.1 and R.sub.2 are each independently hydrogen, oxygen, a hydroxy group (OH), or a linear or branched C.sub.1 to C.sub.10 alkyl group.

A method of forming a silicon-germanium heterojunction bipolar transistor (hbt) device is provided. The method includes forming a stack of four doped semiconductor layers on a semiconductor substrate. The method further includes forming a dummy emitter contact and contact spacers on a fourth doped semiconductor layer of the stack of four doped semiconductor layers, and removing portions of the second, third, and fourth semiconductor layers to form a vertical fin. The method further includes recessing the second and fourth doped semiconductor layers, and depositing a condensation layer on the second, third, and fourth doped semiconductor layers. The method further includes reacting the condensation layer with the third doped semiconductor layer to form a protective segment on a condensed protruding portion.