Embodiments of the present disclosure relates to method of forming trench and via features using dielectric and metal mask layers. Particularly, embodiments of present disclosure provide a hard mask stack including a first dielectric mask layer, and second dielectric mask layer and a metal mask layer, wherein the first dielectric mask layer and second dielectric mask layer have a high etch selectivity.

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a first plurality of conductive interconnect lines in and spaced apart by a first ILD layer, wherein individual ones of the first plurality of conductive interconnect lines comprise a first conductive barrier material along sidewalls and a bottom of a first conductive fill material. A second plurality of conductive interconnect lines is in and spaced apart by a second ILD layer above the first ILD layer, wherein individual ones of the second plurality of conductive interconnect lines comprise a second conductive barrier material along sidewalls and a bottom of a second conductive fill material, wherein the second conductive fill material is different in composition from the first conductive fill material.

The disclosure relates to a sequential infiltration synthesis apparatus comprising: a reaction chamber constructed and arranged to accommodate at least one substrate; a first precursor flow path to provide the first precursor to the reaction chamber when a first flow controller is activated; a second precursor flow path to provide a second precursor to the reaction chamber when a second flow controller is activated; a removal flow path to allow removal of gas from the reaction chamber; a removal flow controller to create a gas flow in the reaction chamber to the removal flow path when the removal flow controller is activated; and, a sequence controller operably connected to the first, second and removal flow controllers and the sequence controller being programmed to enable infiltration of an infiltrateable material provided on the substrate in the reaction chamber. The apparatus may be provided with a heating system.

A method for forming openings in an underlayer includes: forming a photoresist layer on an underlayer formed on a substrate; exposing the photoresist layer; forming photoresist patterns by developing the exposed photoresist layer, the photoresist patterns covering regions of the underlayer in which the openings are to be formed; forming a liquid layer over the photoresist patterns; after forming the liquid layer, performing a baking process so as to convert the liquid layer to an organic layer in a solid form; performing an etching back process to remove a portion of the organic layer on a level above the photoresist patterns; removing the photoresist patterns, so as to expose portions of the underlayer by the remaining portion of the organic layer; forming the openings in the underlayer by using the remaining portion of the organic layer as an etching mask; and removing the remaining portion of the organic layer.

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes first and second gate dielectric layers over a fin. First and second gate electrodes are over the first and second gate dielectric layers, respectively, the first and second gate electrodes both having an insulating cap having a top surface. First dielectric spacer are adjacent the first side of the first gate electrode. A trench contact structure is over a semiconductor source or drain region adjacent first and second dielectric spacers, the trench contact structure comprising an insulating cap on a conductive structure, the insulating cap of the trench contact structure having a top surface substantially co-planar with the insulating caps of the first and second gate electrodes.

Embodiments described herein provide for post deposition anneal of a substrate, having an amorphous carbon layer deposited thereon, to desirably reduce variations in local stresses thereacross. In one embodiment, a method of processing a substrate includes positioning a substrate, having an amorphous carbon layer deposited thereon, in a first processing volume, flowing an anneal gas into the first processing volume, heating the substrate to an anneal temperature of not more than about 450° C., and maintaining the substrate at the anneal temperature for about 30 seconds or more. Herein, the amorphous carbon layer was deposited on the substrate using a method which included positioning the substrate on a substrate support disposed in a second processing volume, flowing a processing gas into the second processing volume, applying pulsed DC power to a carbon target disposed in the second processing volume, forming a plasma of the processing gas, and depositing the amorphous carbon layer on the substrate.

A pellicle for an EUV photo mask includes a first layer, a second layer, and a main membrane disposed between the first layer and second layer. The main membrane includes a plurality of co-axial nanotubes, each of which includes an inner tube and one or more outer tubes surrounding the inner tube, and two of the inner tube and one or more outer tubes are made of different materials from each other.

A method of fabricating a semiconductor device is disclosed. The method may include forming an etch-target layer, a mask layer, a blocking layer, and a photoresist layer, which are sequentially stacked on a substrate; forming a photoresist pattern, the forming the photoresist pattern including irradiating the photoresist layer with extreme ultraviolet (EUV) light; forming a mask layer, the forming the mask layer including etching the mask layer using the photoresist pattern as an etch mask; and forming a target pattern, the forming the target pattern including etching the etch-target layer using the mask pattern as an etch mask. The photoresist layer may include an organic metal oxide. The blocking layer may be a non-polar layer and may limit and/or prevent a metallic element in the photoresist layer from infiltrating into the mask layer.

Embodiments of the present disclosure generally relate to techniques for deposition of high-density films for patterning applications. In one embodiment, a method of processing a substrate is provided. The method includes depositing a carbon hardmask over a film stack formed on a substrate, wherein the substrate is positioned on an electrostatic chuck disposed in a process chamber, implanting ions into the carbon hardmask, wherein depositing the carbon hardmask and implanting ions into the carbon hardmask are performed in the same process chamber, and repeating depositing the carbon hardmask and implanting ions into the carbon hardmask in a cyclic fashion until a pre-determined thickness of the carbon hardmask is reached.

Semiconductor devices and fabrication methods thereof are provided. The method may include forming a first sacrificial film on a to-be-etched layer having; and forming second sacrificial layers on the first sacrificial film. A first trench or a second trench is between adjacent second sacrificial layers; and a width of the second trench is greater than a width of the first trench. The method also includes forming a first sidewall spacer on a sidewall surface of a second sacrificial layer, a ratio between the width of the first trench and a thickness of the first sidewall spacer being greater than 2:1; and etching the first sacrificial film using the first sidewall spacer as an etching mask to form first sacrificial layers. A third trench or a second trench is between adjacent first sacrificial layers. The method also includes forming a second sidewall spacer to fill the third trench.