A method of manufacturing a semiconductor device includes forming an underlying structure in a first area and a second area over a substrate. A first layer is formed over the underlying structure. The first layer is removed from the second area while protecting the first layer in the first area. A second layer is formed over the first area and the second area, wherein the second layer has a smaller light transparency than the first layer. The second layer is removed from the first area, and first resist pattern is formed over the first layer in the first area and a second resist pattern over the second layer in the second area.

A method is provided for fabricating a semiconductor wafer having a device side, a back side opposite the device side and an outer periphery edge. Suitably, the method includes: forming a top conducting layer on the device side of the semiconductor wafer; forming a passivation layer over the top conducting layer, the passivation layer being formed so as not to extend to the outer periphery edge of the semiconductor wafer; and forming a protective layer over the passivation layer, the protective layer being spin coated over the passivation layer so as to have a smooth top surface at least in a region proximate to the outer periphery edge of the semiconductor wafer.

Embodiments of the present disclosure generally relate to techniques for deposition of high-density films for patterning applications. In one embodiment, a method of processing a substrate is provided. The method includes depositing a carbon hardmask over a film stack formed on a substrate, wherein the substrate is positioned on an electrostatic chuck disposed in a process chamber, implanting ions into the carbon hardmask, wherein depositing the carbon hardmask and implanting ions into the carbon hardmask are performed in the same process chamber, and repeating depositing the carbon hardmask and implanting ions into the carbon hardmask in a cyclic fashion until a pre-determined thickness of the carbon hardmask is reached.

A method for forming conductive lines comprises forming a hardmask on an insulator layer, a planarizing layer on the hardmask, and a hardmask on the planarizing layer, removing exposed portions of a layer of sacrificial mandrel material to form first and second sacrificial mandrels on the hardmask, and depositing a layer of spacer material in the gap, and over exposed portions of the first and second sacrificial mandrels and the hardmask. Portions of the layer of spacer material are removed to expose the first and second sacrificial mandrels. A filler material is deposited between the first and second sacrificial mandrels. A portion of the filler material is removed to expose the first and second sacrificial mandrels. Portions of the layer of spacer material are removed to expose portions of the hardmask. A trench is formed in the insulator layer, and the trench is filled with a conductive material.

A semiconductor structure and a method for preparing a semiconductor structure are provided. The method includes: a composite hard mask layer is formed on an etching layer, the composite hard mask layer including a hard mask layer and an etching stop layer surrounded by the hard mask layer; a first target pattern and a first redundant pattern are formed in the composite hard mask layer; a remaining part of the etching stop layer is removed to form a second target pattern and a second redundant pattern in the hard mask layer; etching is performed by using the second target pattern and the second redundant pattern as masks to form a target structure in the etching layer and to form a redundant structure in the hard mask layer; and a remaining part of the hard mask layer is removed.

Embodiments provide method for forming a connecting pad. The method includes: providing a substrate; sequentially forming a conductive layer, a first pattern definition layer and a second pattern definition layer on a surface of the substrate; sequentially forming three groups of patterns intersecting with each other at 120° on the second pattern definition layer, an intersection portion of the three groups of patterns forming a hexagonal pattern definition structure on the second pattern definition layer; transferring the pattern definition structure downward, and etching away a portion of the first pattern definition layer, such that the remaining first pattern definition layer forms a columnar structure, wherein a bottom of the columnar structure is circular in shape under an action of an etching load effect; and etching the conductive layer by using the remaining first pattern definition layer as a mask, such that the remaining conductive layer forms a circular connecting pad.

A method includes receiving an integrated circuit (IC) design layout including a layout block, where the layout block including first line patterns disposed along a first direction, extending lengths of the first line patterns, connecting portions of the first line patterns disposed within a distance less than a preset value, forming second line patterns disposed outside the layout block parallel to the first line patterns, forming mandrel bar patterns overlapping edges of the layout block, where the mandrel bar patterns oriented along a second direction perpendicular to the first direction, and outputting a pattern layout for mask fabricating, where the pattern layout includes the layout block, the first and second line patterns, and the mandrel bar patterns.

A semiconductor device has a semiconductor package including a substrate comprising a land grid array. A component is disposed over the substrate. An encapsulant is deposited over the component. The land grid array remains outside the encapsulant. A fanged metal mask is disposed over the land grid array. A shielding layer is formed over the semiconductor package. The fanged metal mask is removed after forming the shielding layer.

A method of fabricating a semiconductor device includes forming a cut-off region in at least one mandrel line among a plurality of mandrel lines, conformally forming a spacer material layer in the plurality of mandrel lines and a non-mandrel area and forming a cut spacer in the cut-off region and depositing a gap-fill material such that a cut block is formed on a portion of the non-mandrel area and a concave portion of the cut spacer is filled.

A silicon carbide substrate has a trench extending from a main surface of the silicon carbide substrate into the silicon carbide substrate. The trench has a trench width at a trench bottom. A shielding region is formed in the silicon carbide substrate. The shielding region extends along the trench bottom. In at least one doping plane extending approximately parallel to the trench bottom, a dopant concentration in the shielding region over a lateral first width deviates by not more than 10% from a maximum value of the dopant concentration. The first width is less than the trench width and is at least 30% of the trench width.