A method for forming ultra-high density integrated circuitry, such as for a 6T SRAM, for example, is provided. The method involves applying double patterning litho-etch litho-etch (LELE) and using a spacer process to shrink the critical dimension of features. To improve process margins, the method implements a double-patterning technique by modifying the layout and splitting cross-coupling straps into two colors (e.g., each color corresponds to a mask-etch process). In addition, a spacer process is implemented to shrink feature size and increase the metal-to-metal spacing between the two cross-coupling straps, in order to improve process margin and electrical performance. This is achieved by depositing a spacer layer over an opening in a hardmask, followed by spacer etch back. The opening is thus shrunk by the amount of spacer thickness. The strap-to-strap spacing may then be increased by twice the amount of spacer thickness.

The present disclosure, in some embodiments, relates to a method of performing an etch process. The method is performed by forming a first plurality of openings defined by first sidewalls of a mask disposed over a substrate. A cut layer is between two of the first plurality of openings. A spacer is formed onto the first sidewalls of the mask and a second plurality of openings are formed. The second plurality of openings are defined by second sidewalls of the mask and are separated by the spacer. The substrate is etched according to the mask and the spacer.

A semiconductor structure includes: a plurality of calibration reference features disposed on a substrate and spaced apart from each other in a first direction; and a plurality of columns of first active features and a plurality of columns of second active features respectively disposed on opposite sides of the calibration reference features, wherein each of the columns of first active features is spaced apart from each other in a second direction, each of the columns of second active features is spaced apart from each other in the second direction, and the calibration reference features, the first active features, and the second active features are disposed on the same layer and are a portion of the substrate.

A method of defining a pattern includes forming a plurality of cut shapes and a first plurality of openings within a first layer of a multi-layer hard mask to expose first portions of the second layer. A plurality of etch stops is formed by implanting an etch rate modifying species in a portion of the plurality of cut shapes. The first layer is directionally etched at the plurality of cut shapes such that the plurality of etch stops remain. A spacer layer is formed on the first layer and the first portions. A second plurality of openings is formed within the spacer layer to expose second portions of the second layer. The spacer layer is directionally etched to remove the spacer layer from sidewalls of the plurality of etch stops. Portions of the second layer exposed through the first plurality of openings and the second plurality of openings are etched.

A method for forming a pattern can include the following operations. A substrate is provided, on the surface of which a patterned photoresist layer is formed. Based on the photoresist layer, isolation sidewalls are formed, in which each isolation sidewall includes a first sidewall close to the photoresist layer and a second sidewall away from the photoresist layer. Core material layers are formed between two adjacent isolation sidewalls. The second sidewalls are removed to form the pattern composed of the first sidewalls and the core material layers.

A semiconductor structure and a method for preparing a semiconductor structure are provided. The method includes: a composite hard mask layer is formed on an etching layer, the composite hard mask layer including a hard mask layer and an etching stop layer surrounded by the hard mask layer; a first target pattern and a first redundant pattern are formed in the composite hard mask layer; a remaining part of the etching stop layer is removed to form a second target pattern and a second redundant pattern in the hard mask layer; etching is performed by using the second target pattern and the second redundant pattern as masks to form a target structure in the etching layer and to form a redundant structure in the hard mask layer; and a remaining part of the hard mask layer is removed.

An initial semiconductor structure includes an underlying substrate, a hard mask stack, an organic planarization layer (OPL), a first complementary material, and a patterned photoresist layer patterned into a plurality of photoresist pillars defining a plurality of photoresist trenches. The first material is partially etched inward of the trenches, to provide trench regions, and the photoresist is removed. The trench regions are filled with a second complementary material, preferentially etchable with respect to the first material. A polymer brush is grafted on the second material but not the first material, to form polymer brush regions with intermediate regions not covered by the brush. The first material is anisotropically etched the at the intermediate regions but not the brush regions. The OPL is etched inward of the intermediate regions, to provide a plurality of OPL pillars defining a plurality of OPL trenches inverted with respect to the photoresist pillars.

A method for forming a patterned mask layer is provided. The method includes forming a first layer over a substrate. The method includes forming a first strip structure and a second strip structure over the first layer. The method includes forming a spacer layer conformally covering the first strip structure, the second strip structure, and the first layer. The method includes forming a block structure in the first trench. The method includes removing a first portion of the spacer layer, which is under the first trench and not covered by the block structure, and a second portion of the spacer layer, which is over the first strip structure and the second strip structure. The method includes forming a third strip structure in the second trench and the third trench. The method includes removing the block structure. The method includes removing the spacer layer.

A semiconductor device and a method of forming the same, the semiconductor device includes a substrate, a gate structure, a first dielectric layer, a second dielectric layer, a first plug and two metal lines. The substrate has a shallow trench isolation and an active area, and the gate structure is disposed on the substrate to cover a boundary between the active area and the shallow trench isolation. The first dielectric layer is disposed on the substrate, to cover the gate structure, and the first plug is disposed in the first dielectric layer to directly in contact with a conductive layer of the gate structure and the active area. The second dielectric layer is disposed on the first dielectric layer, with the first plug and the gate being entirely covered by the first dielectric layer and the second dielectric layer. The two metal lines are disposed in the second dielectric layer.

Dummy gate patterning lines, and integrated circuit structures resulting therefrom, are described. For example, an integrated circuit structure includes a first gate line along a first direction. A second gate line is parallel with the first gate line along the first direction. A third gate line extends between and is continuous with the first gate line and the second gate line along a second direction, the second direction orthogonal to the first direction.