A photonic structure can include in one aspect one or more waveguides formed by patterning of waveguiding material adapted to propagate light energy. Such waveguiding material may include one or more of silicon (single-, poly-, or non-crystalline) and silicon nitride.

A compound semiconductor has a high electron concentration of 5×10.sup.19 cm.sup.−3 or higher, exhibits an electron mobility of 46 cm.sup.2/V.Math.s or higher, and exhibits a low electric resistance, and thus is usable to produce a high performance semiconductor device. The present invention provides a group 13 nitride semiconductor of n-type conductivity that may be formed as a film on a substrate having a large area size at a temperature of room temperature to 700° C.

A method of forming an interconnect structure for semiconductor devices is described. The method comprises etching a patterned interconnect stack for form first conductive lines and expose a top surface of a first etch stop layer; etching the first etch stop layer to form second conductive lines and expose a top surface of a barrier layer; and forming a self-aligned via.

Methods for preparing epitaxial wafers are disclosed. The methods may involve control of the (i) a growth velocity, v, and/or (ii) an axial temperature gradient, G, during the growth of an ingot segment such that v/G is less than a critical v/G. An epitaxial layer is deposited on a substrate sliced from the silicon ingot.

A method of producing a semiconductor laminate film includes forming a semiconductor layer containing silicon and germanium on a silicon substrate by a sputtering method. In the sputtering method, a film formation temperature of the semiconductor layer is less than 500° C., and a film formation pressure of the semiconductor layer ranges from 1 mTorr to 11 mTorr, or, a film formation temperature of the semiconductor layer is less than 600° C., and a film formation pressure of the semiconductor layer is equal to or more than 2 mTorr and less than 5 mTorr. The sputtering method uses a sputtering gas having a volume ratio of a hydrogen gas of less than 0.1%, and the semiconductor layer satisfies a relationship of t≤0.881×x.sup.−4.79, where t represents a thickness (nm) of the semiconductor layer, and x represents a ratio of the number of germanium atoms to a sum of the number of silicon atoms and the number of germanium atoms in the semiconductor layer.

Processing chamber components and methods of manufacture of same are provided herein. In some embodiments, a component part body includes a component part body having a base plane and at least one textured surface region, wherein the at least one textured surface region comprises a plurality of independent surface features having a first side having at least a 45 degree angle with respect to the base plane. In at least some embodiments, the textured surface includes a plurality of independent surface features which are pore free.

A focus ring adjustment assembly of a system for processing workpieces under vacuum, where the focus ring may include a lower side having a first surface portion and a second surface portion, the first surface portion being vertically above the second surface portion. The adjustment assembly may include a pin configured to selectively contact the first surface portion of the focus ring, and an actuator operable to move the pin along the vertical direction between an extended position and a retracted position. The extended position of the pin may be associated with the distal end of the pin contacting the first surface of the focus ring and the focus ring being accessible for removal by a workpiece handling robot from the vacuum process chamber.

A light-emitting device includes: a substrate; and a laminated structure provided at the substrate and having a plurality of columnar parts. The columnar part has: an n-type first semiconductor layer; a p-type second semiconductor layer; a light-emitting layer provided between the first semiconductor layer and the second semiconductor layer; and an electrode provided on a side opposite to a side of the substrate, of the laminated structure. The first semiconductor layer is provided between the light-emitting layer and the substrate. An end part on a side opposite to a side of the substrate, of the light-emitting layer, has a first facet surface. An end part on a side opposite to a side of the substrate, of the second semiconductor layer, has a second facet surface. A relation of θ2≤θ1 is satisfied, where θ1 is a taper angle of the first facet surface, and θ2 is a taper angle of the second facet surface. θ1 is 70° or smaller, and θ2 is 30° or greater.

A method of forming a semiconductor device including a fin field effect transistor (FinFET) includes forming a first sacrificial layer over a source/drain structure of a FinFET structure and an isolation insulating layer. The first sacrificial layer is patterned, thereby forming an opening. A first liner layer is formed on the isolation insulating layer in a bottom of the opening and on at least side faces of the patterned first sacrificial layer. After the first liner layer is formed, forming a dielectric layer in the opening. After the dielectric layer is formed, removing the patterned first sacrificial layer, thereby forming a contact opening over the source/drain structure. A conductive layer is formed in the contact opening. The FinFET is an n-type FET, and the source/drain structure includes an epitaxial layer including Si.sub.1−x−yM1.sub.xM2.sub.y, where M1 includes Sn, M2 is one or more of P and As, and 0.01≤x≤0.1, and 0.01≤y≤0.1.

Graphite-based devices with a reduced characteristic dimension and methods for forming such devices are provided. One or more thin films are deposited onto a substrate and undesired portions of the deposited thin film or thin films are removed to produce processed elements with reduced characteristic dimensions. Graphene layers are generated on selected processed elements or exposed portions of the substrate after removal of the processed elements. Multiple sets of graphene layers can be generated, each with a different physical characteristic, thereby producing a graphite-based device with multiple functionalities in the same device.