A method includes forming a multi-layer mask over a dielectric layer. Forming the multi-layer mask includes forming a bottom layer over the dielectric layer. A first middle layer is formed over the bottom layer. The first middle layer includes a first silicon-containing material. The first silicon-containing material has a first content of Si—CH.sub.3 bonds. A second middle layer is formed over the first middle layer. The second middle layer includes a second silicon-containing material. The second silicon-containing material has a second content of Si—CH.sub.3 bonds less than the first content of Si—CH.sub.3 bonds.

A tunneling field-effect transistor (TFET) device is disclosed. A frustoconical protrusion structure is disposed over the substrate and protrudes out of the plane of substrate. A drain region is disposed over the substrate adjacent to the frustoconical protrusion structure and extends to a bottom portion of the frustoconical protrusion structure as a raised drain region. A gate stack is disposed over the substrate. The gate stack has a planar portion, which is parallel to the surface of substrate and a gating surface, which wraps around a middle portion of the frustoconical protrusion structure, including overlapping with the raised drain region. An isolation dielectric layer is disposed between the planar portion of the gate stack and the drain region. A source region is disposed as a top portion of the frustoconical protrusion structure, including overlapping with a top portion of the gating surface of the gate stack.

A method includes forming a fin on a substrate. A first liner is formed on the fin. A first dielectric layer is formed above the first liner. A patterned hard mask is formed above the first dielectric layer and has a fin cut opening defined therein. Portions of the first dielectric layer and the first liner disposed below the fin cut opening are removed to expose a portion of the fin. The patterned hard mask layer is removed. The exposed portion of the fin is oxidized to define a diffusion break in the fin.

A method for fabricating a MEMS device includes depositing and patterning a first sacrificial layer onto a silicon substrate, the first sacrificial layer being partially removed leaving a first remaining oxide. Further, the method includes depositing a conductive structure layer onto the silicon substrate, the conductive structure layer making physical contact with at least a portion of the silicon substrate. Further, a second sacrificial layer is formed on top of the conductive structure layer. Patterning and etching of the silicon substrate is performed stopping at the second sacrificial layer. Additionally, the MEMS substrate is bonded to a CMOS wafer, the CMOS wafer having formed thereupon a metal layer. An electrical connection is formed between the MEMS substrate and the metal layer.

A method for manufacturing a semiconductor structure includes depositing a wafer in a processing chamber. Plasma is formed in the processing chamber to process the wafer. A plasma concentration over a peripheral region of the wafer is detected. A plasma distribution over the peripheral region of the wafer is adjusted according to the detected plasma concentration.

A method includes providing a substrate comprising a material layer and a hard mask layer; patterning the hard mask layer to form hard mask lines; forming a spacer layer over the substrate, including over the hard mask lines, resulting in trenches defined by the spacer layer, wherein the trenches track the hard mask lines; forming a antireflective layer over the spacer layer, including over the trenches; forming an L-shaped opening in the antireflective layer, thereby exposing at least two of the trenches; filling the L-shaped opening with a fill material; etching the spacer layer to expose the hard mask lines; removing the hard mask lines; after removing the hard mask lines, transferring a pattern of the spacer layer and the fill material onto the material layer, resulting in second trenches tracking the pattern; and filling the second trenches with a conductive material.

A hard mask and a method of creating thereof are provided. A first layer is deposited that is configured to provide at least one of a chemical and a mechanical adhesion to a layer immediately below it. A second layer is deposited having an etch selectivity that is faster than the first layer. A third layer is deposited having an etch selectivity that is slower than the first and second layers. The third layer has a composite strength that is higher than the first and second layers. A photoresist layer is deposited on top of the third layer and chemically removed above an inner opening. The third layer and part of the second layer are anisotropically etched through the inner opening. The second layer and the first layer are isotropically etched to create overhang regions of the third layer.

A method includes providing a substrate comprising a material layer and a hard mask layer; patterning the hard mask layer to form hard mask lines; forming a spacer layer over the substrate, including over the hard mask lines, resulting in trenches defined by the spacer layer, wherein the trenches track the hard mask lines; forming a antireflective layer over the spacer layer, including over the trenches; forming an L-shaped opening in the antireflective layer, thereby exposing at least two of the trenches; filling the L-shaped opening with a fill material; etching the spacer layer to expose the hard mask lines; removing the hard mask lines; after removing the hard mask lines, transferring a pattern of the spacer layer and the fill material onto the material layer, resulting in second trenches tracking the pattern; and filling the second trenches with a conductive material.

Techniques herein include an etch process that etches a layer of material incrementally, similar to mono-layer etching of atomic layer etching (ALE), but not necessarily including self-limiting, mono-layer action of ALE. Such techniques can be considered as quasi-atomic layer etching (Q-ALE). Techniques herein are beneficial to precision etching applications such as during soft-mask open. Techniques herein enable precise transfer of a given mask pattern into an underlying layer. By carefully controlling the polymer deposition relative to polymer assisted etching through its temporal cycle, a very thin layer of conformal polymer can be activated and used to precisely etch and transfer the desired patterns.

A method for forming conductive lines comprises forming a hardmask on an insulator layer, a planarizing layer on the hardmask, and a hardmask on the planarizing layer, removing exposed portions of a layer of sacrificial mandrel material to form first and second sacrificial mandrels on the hardmask, and depositing a layer of spacer material in the gap, and over exposed portions of the first and second sacrificial mandrels and the hardmask. Portions of the layer of spacer material are removed to expose the first and second sacrificial mandrels. A filler material is deposited between the first and second sacrificial mandrels. A portion of the filler material is removed to expose the first and second sacrificial mandrels. Portions of the layer of spacer material are removed to expose portions of the hardmask. A trench is formed in the insulator layer, and the trench is filled with a conductive material.