A transistor including an oxide semiconductor layer can have stable electrical characteristics. In addition, a highly reliable semiconductor device including the transistor is provided. A semiconductor device includes a multi-layer film including an oxide layer and an oxide semiconductor layer, a gate insulating film in contact with the multi-layer film, and a gate electrode overlapping with the multi-layer film with the gate insulating film provided therebetween. In the semiconductor device, the oxide semiconductor layer contains indium, the oxide semiconductor layer is in contact with the oxide layer, and the oxide layer contains indium and has a larger energy gap than the oxide semiconductor layer.

A semiconductor device comprises a first semiconductor fin having a first width, the first semiconductor fin is arranged on a first portion of the strain relaxation buffer layer, where the first portion of the strain relaxation buffer layer has a second width and a second semiconductor fin having a width substantially similar to the first width, the second semiconductor fin is arranged on a second portion of the strain relaxation buffer layer, where the second portion of the strain relaxation buffer layer has a third width. A gate stack is arranged over a channel region of the first fin and a channel region of the second fin.

In some aspects of the invention, an n-type field-stop layer can have a total impurity of such an extent that a depletion layer spreading in response to an application of a rated voltage stops inside the n-type field-stop layer together with the total impurity of an n.sup.− type drift layer. Also, the n-type field-stop layer can have a concentration gradient such that the impurity concentration of the n-type field-stop layer decreases from a p.sup.+ type collector layer toward a p-type base layer, and the diffusion depth is 20 μm or more. Furthermore, an n.sup.+ type buffer layer of which the peak impurity concentration can be higher than that of the n-type field-stop layer at 6×10.sup.15 cm.sup.−3 or more, and one-tenth or less of the peak impurity concentration of the p.sup.+ type collector layer, can be included between the n-type field-stop layer and p.sup.+ type collector layer.

A photodiode has a substrate. A mesa structure is formed on the substrate, wherein the mesa structure has an n region containing an n type dopant formed on the substrate, an intermediate region positioned on the n region and a p region formed on the intermediate region and containing a p type dopant. A contact is formed on a top surface of the mesa and attached to the p region. The contact is formed around an outer perimeter of the mesa. The mesa has a diameter of 30 um or less.

To improve the withstand capability of a transistor portion, provided is a semiconductor device including a semiconductor substrate; a transistor portion provided in the semiconductor substrate; and a diode portion provided in the semiconductor substrate and arranged adjacent to the transistor portion in a predetermined arrangement direction. The transistor portion includes a collector region provided in a bottom surface of the semiconductor substrate, at respective ends adjacent to the diode portion; and a first low injection region that is provided on a bottom surface side of the semiconductor substrate farther inward than the respective ends, and has a carrier injection density from the bottom surface side to a top surface side of the semiconductor substrate that is lower than that of the collector region.

A method of making stacked lateral semiconductor devices is disclosed. The method includes depositing a stack of alternating layers of different materials. Slots or holes are cut through the layers for subsequent formation of single crystal semiconductor fences or pillars. When each of the alternating layers of one material are removed space is provided for formation of single crystal semiconductor devices between the remaining layers. The devices are doped as the single crystal silicon is formed.

A method for fabricating a semiconductor device includes forming a channel region in a semiconductor substrate. The channel region is made of a first material. The method also includes forming source and drain regions in the semiconductor substrate. The method further includes forming a recess between the channel region and the drain region. The method further includes forming a tunnel barrier layer in the recess. The tunnel barrier layer is made of a second material, and a bandgap of the second material is greater than a bandgap of the first material. The method further includes forming a gate stack on the channel region.

A manufacturing method of a touch panel includes following steps. The first sensing electrodes and the second sensing electrodes are formed on a substrate first. Connecting bridges are formed next, wherein adjacent two first sensing electrodes are connected by at least one connecting bridge, and a manufacturing method of the connecting bridges includes following steps. A metal layer is formed on the substrate first, wherein a material of the metal layer includes silver. A photoresist layer is formed on a surface of the metal layer next, wherein a material of the photoresist layer includes sulfur. A photolithography process and an etching process are respectively performed on the photoresist layer and the metal layer to form the connecting bridges, wherein silver in the metal layer and sulfur in the photoresist layer react with each other to form a silver sulfide layer after the photoresist layer is formed.

An insulated gate turn-off thyristor has a layered structure including a p+ layer (e.g., a substrate), an n-epi layer, a p-well, vertical insulated gate regions formed in the p-well, and an n layer over the p-well and between the gate regions, so that vertical npn and pnp transistors are formed. After forming the p-well, boron ions are implanted into the exposed surface of the p-well to form a p+ region. The n-epi layer is then grown over the p-well and the p+ region, and the boron in the p+ region is diffused upward into the n-epi layer and downward to form an intermediate p+ region. The p-well's highly doped intermediate region enables improvement in the npn transistor efficiency as well as enabling more independent control over the characteristics of the n-type layer (emitter) and the overall dopant concentration and thickness of the p-type base to optimize the thyristor's performance.

Methods of forming microelectronic package structures, and structures formed thereby, are described. Those methods/structures may include attaching a die on a board, attaching a substrate on the die, wherein the substrate comprises a first region and a peripheral region, attaching a first memory device on the central region of the substrate, and attaching at least one additional memory device on the peripheral region of the substrate, wherein the at least one additional memory device is not disposed over the die.