A trench having an opening and a corner portion is formed in a silicon carbide substrate. A corner insulating film is formed to cover the corner portion. A gate insulating film is formed to cover a region extending from the opening to the corner portion. The step of forming the gate insulating film includes a step of thermally oxidizing the trench provided with the corner insulating film. The step of thermally oxidizing the trench includes a step of heating the silicon carbide substrate at not less than 1300° C. Accordingly, sufficient insulation reliability of the gate insulating film is secured near the opening of the trench while preventing dielectric breakdown of the gate oxide film at the bottom portion of the trench.

A method of forming a strained channel for a field effect transistor, including forming a sacrificial layer on a substrate, forming a channel layer on the sacrificial layer, forming a stressor layer on the channel layer, wherein the stressor layer applies a stress to the channel layer, forming at least one etching trench by removing at least a portion of the stressor layer, channel layer, and sacrificial layer, wherein the etching trench exposes at least a portion of a sidewall of the sacrificial layer, and separates the stressor layer, channel layer, and sacrificial layer into two or more stressor islands, channel blocks, and sacrificial slabs, and removing the sacrificial slabs to release the channel blocks from the substrate using a selective etch, wherein the channel blocks adhere to the substrate surface.

A light emitting diode module includes a substrate, a first soldering section, a second soldering section, a block and a light emitting diode die. The substrate has a top surface and includes a circuit structure. The block is formed on the top surface. The soldering section and the second solder section are formed on the top surface of the substrate and electrically connected with the circuit structure. The block is positioned between the first soldering section and the second solder section. A height of the block is larger than thicknesses of the first soldering section and the second soldering section. The light emitting diode die includes a first electrode and a second electrode being respectively electrically connected to the first soldering section and the second soldering section. The block is positioned between the first soldering section and the second soldering section.

A method of fabricating features of a semiconductor device includes forming a contact over a substrate, the contact including a cobalt core and a liner layer arranged on sidewalls, wherein the contact includes a portion that is laterally surrounded by an interlevel dielectric (ILD); depositing another layer of ILD on the contact; etching a first opening in the ILD to expose a surface of the contact; removing the liner layer of the contact to expose a portion of the cobalt core; etching the ILD that laterally surrounds the contact to form a second opening beneath the first opening, the second opening having a width that is less than the first opening; depositing a liner on sidewalls of the first opening, the second opening, and directly on the cobalt core; and depositing a metal on the liner layer to form an interconnect structure.

Techniques are disclosed for customization of fin-based transistor devices to provide a diverse range of channel configurations and/or material systems within the same integrated circuit die. In accordance with one example embodiment, sacrificial fins are removed and replaced with custom semiconductor material of arbitrary composition and strain suitable for a given application. In one such case, each of a first set of the sacrificial fins is recessed or otherwise removed and replaced with a p-type material, and each of a second set of the sacrificial fins is recessed or otherwise removed and replaced with an n-type material. The p-type material can be completely independent of the process for the n-type material, and vice-versa. Numerous other circuit configurations and device variations are enabled using the techniques provided herein.

A method of controlling an effective gate length in a vertical field effect transistor is provided. The method includes forming a vertical fin on a substrate, and forming a bottom spacer layer on the substrate adjacent to the vertical fin. The method further includes forming a dummy gate block adjacent to the vertical fin on the bottom spacer layer. The method further includes forming a top spacer adjacent to the vertical fin on the dummy gate block, and removing the dummy gate block to expose a portion of the vertical fin between the top spacer and bottom spacer layer. The method further includes forming an absorption layer on the exposed portion of the vertical fin. The method further includes heat treating the absorption layer and vertical fin to form a dopant modified absorption layer, and removing the dopant modified absorption layer.

A method for forming a semiconductor device structure is provided. The method includes depositing a gate dielectric layer over a substrate. The substrate has a base portion and a first fin portion over the base portion, and the gate dielectric layer is over the first fin portion. The method includes forming a gate electrode layer over the gate dielectric layer. The gate electrode layer includes fluorine. The method includes annealing the gate electrode layer and the gate dielectric layer so that fluorine from the gate electrode layer diffuses into the gate dielectric layer.

A semiconductor device includes a transistor implemented over an oxide layer, one or more electrical connections to the transistor, one or more dielectric layers formed over at least a portion of the electrical connections, an electrical element disposed over the one or more dielectric layers, the electrical element being in electrical communication with the transistor via the one or more electrical connections, a patterned form of sacrificial material covering at least a portion of the electrical element, and an interface layer covering at least a portion of the one or more dielectric layers and the sacrificial material.

A method for fabricating a radio-frequency device involves providing a semiconductor wafer including a transistor device, applying a form of sacrificial material on the semiconductor wafer, applying an interface material over the form of sacrificial material, and removing at least a portion of the form of sacrificial material to form a cavity at least partially covered by the interface material.

A method for fabricating a semiconductor die involves providing a semiconductor substrate, forming a plurality of active devices and a plurality of passive devices over the semiconductor substrate, forming one or more electrical connections to the plurality of active devices and the plurality of passive devices, forming one or more dielectric layers over at least a portion of the electrical connections, applying an interface material over at least a portion of the one or more dielectric layers, removing portions of the interface material to form a plurality of trenches, and covering at least a portion of the interface material and the plurality of trenches with a substrate layer to form a plurality of radio-frequency isolation cavities.