Embodiments herein describe techniques for a semiconductor device including a memory cell vertically above a substrate. The memory cell includes a metal-insulator-metal (MIM) capacitor at a lower device portion, and a transistor at an upper device portion above the lower device portion. The MIM capacitor includes a first plate, and a second plate separated from the first plate by a capacitor dielectric layer. The first plate includes a first group of metal contacts coupled to a metal electrode vertically above the substrate. The first group of metal contacts are within one or more metal layers above the substrate in a horizontal direction in parallel to a surface of the substrate. Furthermore, the metal electrode of the first plate of the MIM capacitor is also a source electrode of the transistor. Other embodiments may be described and/or claimed.

The present application discloses an OTP memory. A cell structure includes a first active region and a second active region that intersect vertically; an EDNMOS is formed in the first active region, and a PMOS is formed in the second active region; a body portion of a channel region of the PMOS is formed a drift region of the EDNMOS, a first polysilicon gate of the EDNMOS serves as a control gate, and a second polysilicon gate of the PMOS serves as a floating gate; and the PMOS is programmed by means of hot carriers generated in the drift region of the EDNMOS. The present application further discloses a method for manufacturing an OTP memory. In the present application, high-speed writing can be implemented.

A source electrode (5), a drain electrode (6) and a T-shaped gate electrode (9) are formed on a GaN-based semiconductor layer (3,4) to form a transistor. An insulating film (10,11) covering the T-shaped gate electrode (9) is formed. A property of the transistor is evaluated to obtain an evaluation result. A film type, a film thickness or a dielectric constant of the insulating film (10,11) is adjusted in accordance with the evaluation result to make a property of the transistor close to a target property.

Semiconductor devices and methods of manufacturing the same are described. The methods form a 3D DRAM architecture that includes a semiconductor isolation bridge, eliminating a floating body effect. The method includes forming an epitaxial layer in a deep trench isolation opening and creating a semiconductor isolation bridge between adjacent deep trench isolation openings.

A semiconductor device includes an extremely thin semiconductor-on-insulator substrate (ETSOI) having a base substrate, a thin semiconductor layer and a buried dielectric therebetween. A device channel is formed in the thin semiconductor layer. Source and drain regions are formed at opposing positions relative to the device channel. The source and drain regions include an n-type material deposited on the buried dielectric within a thickness of the thin semiconductor layer. A gate structure is formed over the device channel.

An MOSFET manufacturing method, comprising: etching an oxide layer and a silicon nitride layer on a first conductivity type well region, and forming an opening exposing the first conductivity type well region; etching the first conductivity type well region to form a first trench; depositing a medium oxide layer and performing back etching; etching the first conductivity type well region to form a second trench that is connected to the first trench, and forming a grid on an inner wall of the second trench, forming a second conductivity type well region in the first conductivity type well region at the bottom of the second trench, and forming a source in the second conductivity type well region; and removing the oxide layer and the silicon nitride layer, and forming a drain at the first conductivity type well region outside of the trench.

Some embodiments include an integrated assembly having a laterally-extending container-shaped first capacitor electrode, and having a laterally-extending container-shaped second capacitor electrode laterally offset from the first capacitor electrode. Capacitor dielectric material lines interior surfaces and exterior surfaces of the container-shaped first and second capacitor electrodes. A shared capacitor electrode extends vertically between the first and second capacitor electrodes, and extends along the lined interior and exterior surfaces of the first and second capacitor electrodes. Some embodiments include methods of forming integrated assemblies.

The present invention relates to a specific method step (channel hole etching) in the production of a three-dimensionally integrated semiconductor memory. According to the invention, this method step is characterized in that the vertical channel structure to be generated thereby, the so-called channel hole, is generated by applying an anodic etching method. Thereby, layer stacks having significantly more individual layers than in conventional technology can be processed. Accordingly, the number of individual layers within a layer stack to be processed can be increased, whereby the memory capacity of the layer stack can also be increased significantly.

The concept relates to a method for producing a three-dimensionally integrated semiconductor memory. A layer stack having several individual layers of different material types is provided and individual layers of a first material type are etched out selectively from the layer stack by a dry etching process. Individual layers of a third material type are generated either by filling voids with a third material or converting the individual layers of the second material type into the individual layers of the third material type, or by coating the individual layers of the second material type with a material of the third material type. Voids between the individual layers of the third material type can then again be filled with a fourth material, such that individual layers of a fourth material type are formed in these voids.

The Rds*Cgd figure of merit (FOM) of a laterally diffused metal oxide semiconductor (LDMOS) transistor is improved by forming the drain drift region with a number of dopant implants at a number of depths, and forming a step-shaped back gate region with a number of dopant implants at a number of depths to adjoin the drain drift region.