Patent classifications
H01L21/67282
INSPECTION DEVICE AND INSPECTION METHOD
This inspection device includes: a laser irradiation unit that irradiates a wafer having a back surface and a front surface with a laser beam from the back surface side of the wafer; an imaging unit that outputs light having permeability to the wafer and detects the light propagating through the wafer; and a control part configured to perform a first process of controlling the laser irradiation unit so that a modified region is formed inside the wafer by irradiating the wafer with the laser beam and a second process of deriving a position of the modified region on the basis of a signal output from the imaging unit that detects the light and deriving a thickness of the wafer on the basis of the derived position of the modified region and a set recipe.
Laser marking device and laser marking method
A laser marking device includes a laser emission unit configured to emit a laser beam to a first surface of an object to be processed, and a pressing unit configured to press a second surface that is opposite to the first surface of the object to be processed to make the first surface of the object to be flat. The pressing unit includes a first pressing portion configured to press an edge area of the second surface in a contact manner, and at least one second pressing portion configured to press a middle area of the second surface in a non-contact manner to maintain a separation distance from the second surface within a certain distance.
LASER DICING SYSTEM AND METHOD FOR DICING SEMICONDUCTOR STRUCTURE
A laser dicing system is disclosed. The laser dicing system includes a host device and a laser source. The host device reads and identifies a mark formed on a surface of a semiconductor structure. The laser source is coupled to the host device and is configured to generate a dicing laser energy to form a trench on the semiconductor structure. The dicing laser energy irradiated on the semiconductor structure is adjustable based on information embedded in the mark.
Secure inspection and marking of semiconductor wafers for trusted manufacturing thereof
A method for securing and verifying semiconductor wafers during fabrication includes receiving a semiconductor wafer after a layer of features has been patterned thereon. At least one security mark is formed at one or more locations embedded within a backside of the semiconductor wafer by implanting an inert species at the one or more locations. At a subsequent point in fabrication and/or after fabrication of the semiconductor wafer has completed the backside of the wafer is inspected for detection of the at least one security mark. If the at least one security mark is not detected at an expected location within the backside of the semiconductor wafer a determination is made that the semiconductor wafer has been compromised.
WAFER PROCESSING SYSTEM
A wafer processing system includes a laser processing apparatus, a grinding apparatus, a tape sticking apparatus, a first cassette placement part, a second cassette placement part, a conveying unit that conveys a wafer, and a controller that controls the respective constituent elements. The controller includes a first processing program instructing section that conveys a wafer unloaded from a first cassette in order of the laser processing apparatus, the grinding apparatus, the tape sticking apparatus, and a second cassette and sequentially carries out processing by each apparatus for the one wafer, and a second processing program instructing section that conveys the wafer unloaded from the first cassette in order of the grinding apparatus, the laser processing apparatus, the tape sticking apparatus, and the second cassette and sequentially carries out processing by each apparatus for the one wafer.
Inspection system and method for inspecting semiconductor package, and method of fabricating semiconductor package
An inspection system for a semiconductor package includes an inspection apparatus that includes a stage on which the semiconductor package is loaded, and a computer coupled to the inspection apparatus. The semiconductor package may include a first semiconductor chip and a second semiconductor chip on the first semiconductor chip, the computer may provide first identification information about the first semiconductor chip and second identification information about the second semiconductor chip, and the computer may control the inspection apparatus to selectively perform a package test process on one of the first and second semiconductor chips, the one of the first and second semiconductor chips being identified as a good chip based on the first identification information and the second identification information.
Substrate processing apparatus, method for manufacturing semiconductor device, method for processing substrates
A substrate supporting member provided in a processing chamber for processing the substrate and configured to support the substrate, has on its upper surface, a protruding area that supports an edge side of the substrate from below; a recessed area provided inside of the protruding area so as not to be brought into contact with the substrate supported by the protruding area; and an auxiliary protruding area formed lower than the protruding area and provided in the recessed area, and has a flow passage that is communicated with inside of the recessed area, for escaping gas between the substrate and the substrate supporting member from the recessed area side.
SECURE INSPECTION AND MARKING OF SEMICONDUCTOR WAFERS FOR TRUSTED MANUFACTURING THEREOF
A method for securing and verifying semiconductor wafers during fabrication includes receiving a semiconductor wafer after a layer of features has been patterned thereon. At least one security mark is formed at one or more locations embedded within a backside of the semiconductor wafer by implanting an inert species at the one or more locations. At a subsequent point in fabrication and/or after fabrication of the semiconductor wafer has completed the backside of the wafer is inspected for detection of the at least one security mark. If the at least one security mark is not detected at an expected location within the backside of the semiconductor wafer a determination is made that the semiconductor wafer has been compromised.
SYSTEM AND METHOD FOR ALIGNMENT OF AN INTEGRATED CIRCUIT
The integrated circuit assembly can include: a semiconductor and a substrate (e.g., PCB). The integrated circuit assembly can optionally include: a compliant connector, a thermal management, and a securing element. The semiconductor 210 can include a first alignment feature. (e.g., orifice). The substrate can include a second alignment feature (e.g., alignment target) and conductive pads. The substrate can optionally include a cavity.
MATERIAL PROCESSING METHOD AND MATERIAL PROCESSING SYSTEM FOR PERFORMING THE METHOD
A material processing system includes a particle beam column for directing a particle beam at a first processing region and a laser scanner for directing a laser beam at a second processing region. A method for operating the material processing system includes: scanning a first mark placed on an object with the particle beam; scanning the first mark with the laser beam for a first time and producing a second mark on the object with the laser beam; scanning the second mark with the particle beam; and scanning the first mark with the laser beam for a second time and removing material of the object with the laser beam based on the scanning of the second mark with the particle beam.