Methods for etching a semiconductor structure and for conditioning a processing reactor in which a single semiconductor structure is treated are disclosed. An engineered polycrystalline silicon surface layer is deposited on a susceptor which supports the semiconductor structure. The polycrystalline silicon surface layer may be engineered by controlling the temperature at which the layer is deposited, by grooving the polycrystalline silicon surface layer or by controlling the thickness of the polycrystalline silicon surface layer.

A system includes a robot configured to transfer either one of a substrate and an edge ring within a substrate processing system, a substrate aligner configured to adjust a rotational position of either one of the substrate or the edge ring relative to an end effector of the robot, and a carrier plate configured to support the edge ring. The robot is configured to retrieve the carrier plate with the end effector, retrieve the edge ring using the carrier plate supported on the end effector, and transfer the carrier plate and the edge ring to the substrate aligner.

A substrate holder for use in a lithographic apparatus and configured to support a substrate, the substrate holder including a main body having a main body surface; a plurality of burls projecting from the main body surface to support the substrate spaced apart from the main body surface; and a liquid control structure provided in a peripheral region of the main body surface and configured to cause liquid to preferentially flow toward the periphery of the main body surface.

Embodiments of deposition rings for use in a process chamber are provided herein. In some embodiments, a deposition ring includes: an annular body; an inner wall extending upward from an inner portion of the annular body; and an outer wall extending upward form an outer portion of the annular body to define a large deposition cavity between the inner wall and the outer wall, wherein a width of the large deposition cavity is about 0.35 inches to about 0.60 inches, wherein the outer wall includes an outer ledge and an inner ledge raised with respect to the outer ledge.

The present invention relates to a component for manufacturing a semiconductor manufactured by using a CVD method. A SiC structure formed by the CVD method according to one aspect of the present invention is used such that the SiC structure is exposed to plasma inside a chamber, wherein the SiC structure comprises a crystal grain structure in which the length in a first direction is longer than the length in a second direction when defining a direction perpendicular to the surface most exposed to the plasma as the first direction and a direction horizontal to the surface most exposed to the plasma as the second direction.

An exclusion ring for semiconductor wafer processing includes an outer circumferential segment having a first thickness and an inner circumferential segment having a second thickness, with the first thickness being greater than the second thickness. The top surface of an inner circumferential segment and the top surface of the outer circumferential segment define a common top surface for the exclusion ring. A plurality of flow paths is formed within the outer circumferential segment, with each of the flow paths extending radially through the plurality of flow paths provides for exhaust of a wafer edge gas from the pocket where a wafer has an edge thereof disposed below part of the inner circumferential portion. The exhausting of the wafer edge gas from the pocket prevents up-and-down movement of the exclusion ring when bowed wafers are processed.

Susceptor assemblies comprising a susceptor base and a plurality of pie-shaped skins thereon are described. A pie anchor can be positioned in the center of the susceptor base to hold the pie-shaped skins in place during processing.

According to one embodiment, an electrostatic chuck includes a ceramic dielectric substrate, a base plate, and first and second electrode layers. The ceramic dielectric substrate includes first and second major surfaces. The first and second electrode layers are provided inside the ceramic dielectric substrate. The second electrode layer is provided between the first electrode layer and the first major surface. The first electrode layer includes first and second portions. The first portion is positioned more centrally of the ceramic dielectric substrate than is the second portion. The first portion includes first and second surfaces. The second portion includes third and fourth surfaces. The third surface is positioned between the first surface and the second electrode layer. An electrical resistance of the first surface is less than an average electrical resistance of the first portion.

A substrate bonding apparatus includes a first bonding chuck configured to support a first substrate and a second bonding chuck configured to support a second substrate such that the second substrate faces the first substrate. The first bonding chuck includes a first base, a first deformable plate on the first base and configured to support the first substrate and configured to be deformed such that a distance between the first base and the first deformable plate is varied, and a first piezoelectric sheet on the first deformable plate and configured to be deformed in response to power applied thereto to deform the first deformable plate.

Embodiments of the invention generally relate to a process kit for a semiconductor processing chamber, and a semiconductor processing chamber having a kit. More specifically, embodiments described herein relate to a process kit including a deposition ring and a pedestal assembly. The components of the process kit work alone, and in combination, to significantly reduce their effects on the electric fields around a substrate during processing.