A method includes depositing an interlayer dielectric (ILD) over a source/drain region, implanting impurities into a portion of the ILD, recessing the portion of the ILD to form a trench, forming spacers on sidewalls of the trench, the spacers including a spacer material, forming a source/drain contact in the trench and removing the spacers and the portion of the ILD with an etching process to form an air-gap, the air-gap disposed under and along sidewalls of the source/drain contact, where the etching process selectively etches the spacer material and the impurity.

Devices and structures that include a gate spacer having a gap or void are described along with methods of forming such devices and structures. In accordance with some embodiments, a structure includes a substrate, a gate stack over the substrate, a contact over the substrate, and a spacer disposed laterally between the gate stack and the contact. The spacer includes a first dielectric sidewall portion and a second dielectric sidewall portion. A void is disposed between the first dielectric sidewall portion and the second dielectric sidewall portion.

There is provided a solid-state imaging device including: one or more photoelectric conversion elements provided on side of a first surface of a semiconductor substrate; a through electrode coupled to the one or more photoelectric conversion elements, and provided between the first surface and a second surface of the semiconductor substrate; and an amplifier transistor and a floating diffusion provided on the second surface of the semiconductor substrate, in which the one or more photoelectric conversion elements are coupled to a gate of the amplifier transistor and the floating diffusion via the through electrode.

A semiconductor device includes a substrate, a first conductive feature over a portion of the substrate, and an etch stop layer over the substrate and the first conductive feature. The etch stop layer includes a silicon-containing dielectric (SCD) layer and a metal-containing dielectric (MCD) layer over the SCD layer. The semiconductor device further includes a dielectric layer over the etch stop layer, and a second conductive feature in the dielectric layer. The second conductive feature penetrates the etch stop layer and electrically connects to the first conductive feature.

In various embodiments a method for manufacturing a metallization layer on a substrate is provided, wherein the method may include providing a structured layer of a catalyst material on the substrate, the catalyst material may include a first layer of material arranged over the substrate and a second layer of material arranged over the first layer of material, wherein the structured layer of catalyst material having a first set of regions including the catalyst material over the substrate and a second set of regions free of the catalyst material over the substrate, and forming a plurality of groups of nanotubes over the substrate, each group of the plurality of groups of nanotubes includes a plurality of nanotubes formed over a respective region in the first set of regions.

Middle-of-line (MOL) interconnects that facilitate reduced capacitance and/or resistance and corresponding techniques for forming the MOL interconnects are disclosed herein. An exemplary MOL interconnect structure includes a device-level contact disposed in a first insulator layer and a ruthenium structure disposed in a second insulator layer disposed over the first insulator layer. The device-level contact physically contacts an integrated circuit feature, and the ruthenium structure physically contacts the device-level contact. An air gap separates sidewalls of the ruthenium structure from the second insulator layer. A top surface of the ruthenium structure is lower than a top surface of the second insulator layer. A via disposed in a third insulator layer extends below the top surface of the second insulator layer to physically contact the ruthenium structure. A remainder of a dummy contact spacer layer may separate the first insulator layer and the second insulator layer.

A method for fabricating semiconductor device includes the steps of: forming a dielectric layer on a substrate; forming a stop layer between the dielectric layer and the substrate, wherein the stop layer contacts the substrate directly and the dielectric layer covers the top surface of the stop layer; forming an opening in the dielectric layer, wherein the dielectric layer comprises a damaged layer adjacent to the opening; forming a dielectric protective layer in the opening; forming a metal layer in the opening; removing the damaged layer and the dielectric protective layer to form a void, wherein the void exposes a top surface of the substrate; and forming a cap layer on and covering the dielectric layer, the void, and the metal layer.

A method for depositing a film to form an air gap within a semiconductor device is disclosed. An exemplary method comprises pulsing a metal halide precursor onto the substrate and pulsing an oxygen precursor onto a selective deposition surface. The method can be used to form an air gap to, for example, reduce a parasitic resistance of the semiconductor device.

In a method of manufacturing a semiconductor memory device, a plurality of first conductive structures including a first conductive pattern and a hard mask are sequentially stacked on a substrate. A plurality of preliminary spacer structures including first spacers, sacrificial spacers and second spacers are sequentially stacked on sidewalls of the conductive structures. A plurality of pad structures are formed on the substrate between the preliminary spacer structures, and define openings exposing an upper portion of the sacrificial spacers. A first mask pattern is formed to cover surfaces of the pad structures, and expose the upper portion of the sacrificial spacers. The sacrificial spacers are removed to form first spacer structures having respective air spacers, and the first spacer structures include the first spacers, the air spacers and the second spacers sequentially stacked on the sidewalls of the conductive structures.

A metallization stack and a method of manufacturing the same, and an electronic device including the metallization stack are provided. The metallization stack may include at least one interconnection line layer and at least one via hole layer arranged alternately on a substrate. At least one pair of adjacent interconnection line layer and via hole layer in the metallization stack includes: an interconnection line in the interconnection line layer, and a via hole in the via hole layer. The interconnection line layer is closer to the substrate than the via hole layer. A peripheral sidewall of a via hole on at least part of the interconnection line does not exceed a peripheral sidewall of the at least part of the interconnection line.