An embodiment of a semiconductor device includes a plate line that is connected to ferroelectric capacitors selected from a plurality of ferroelectric capacitors and covers the selected ferroelectric capacitors and regions between the selected ferroelectric capacitors from above top electrodes.

The present application provides a dual-port SRAM cell and a layout structure thereof, comprises a first and a second NMOS transistors, a first and a second PMOS transistors; the gates of the first and second NMOS transistors and the drains of the first and second PMOS transistors are connected to a word line; the source of the first NMOS transistor is connected to a first bit line; the source of the first PMOS transistor is connected to a second bit line; the source of the second NMOS transistor is connected to a third bit line; the source of the second PMOS transistor is connected to a fourth bit line; the drain of the first NMOS transistor and the gate of the first PMOS transistor are connected to a common input node of a latch.

A 3D semiconductor device, the device including: a first level including a plurality of first single crystal transistors and a first metal layer, where the first transistors include forming memory control circuits; a second level including a plurality of second transistors; a third level including a plurality of third transistors, where the second level is above the first level, and where the third level is above the second level; a second metal layer above the third level; and a third metal layer above the second metal layer, where the second transistors are aligned to the first transistors with less than 140 nm alignment error, where the second level includes a plurality of first memory cells, where the third level includes a plurality of second memory cells, and where the memory control circuits are designed to adjust a memory write voltage according to the device specific process parameters.

A memory circuit according to an embodiment includes: a first inverter circuit including a first p-channel MOS transistor and a first n-channel MOS transistor; a second inverter circuit cross-coupled with the first inverter and including a second p-channel MOS transistor and a second n-channel MOS transistor; a third n-channel MOS transistor in which one of a source and drain terminals is connected to a first output terminal of the first inverter circuit, and a gate terminal is connected to a first wiring line; a fourth n-channel MOS transistor connected to the third n-channel MOS transistor; a fifth n-channel MOS transistor in which one of a source and drain terminals is connected to a second output terminal of the second inverter circuit; and a sixth n-channel MOS transistor connected to the fifth n-channel MOS transistor.

A device comprises a first inverter comprising a first p-type transistor (PU) and a first n-type transistor (PD), a second inverter cross-coupled to the first inverter comprising a second PU and a second PD, a first pass-gate transistor coupled between the first inverter and a first bit line and a second pass-gate transistor coupled between the second inverter and a second bit line, wherein at least one transistor has a two-stage fin structure, and wherein a width of a bottom portion of the two-stage fin structure is greater than a width of an upper portion of the two-stage fin structure.

A device includes a first semiconductor strip, a first gate dielectric encircling the first semiconductor strip, a second semiconductor strip overlapping the first semiconductor strip, and a second gate dielectric encircling the second semiconductor strip. The first gate dielectric contacts the first gate dielectric. A gate electrode has a portion over the second semiconductor strip, and additional portions on opposite sides of the first and the second semiconductor strips and the first and the second gate dielectrics.

An inductive capacitive structure including a first substrate, a first conductive line over the first substrate, a first shielding layer over the first substrate and a second substrate over the first substrate.

An integrated circuit structure includes a semiconductor substrate including a first portion in a first device region, and a second portion in a second device region. A first semiconductor fin is over the semiconductor substrate and has a first fin height. A second semiconductor fin is over the semiconductor substrate and has a second fin height. The first fin height is greater than the second fin height.

Methods of depositing silicon nitride encapsulation layers by atomic layer deposition over memory devices including chalcogenide material are provided herein. Methods include using iodine-containing silicon precursors and depositing thermally using ammonia or hydrazine as a second reactant, or iodine-containing silicon precursors and depositing using a nitrogen-based or hydrogen-based plasma.

An integrated circuit device may include the following elements: a first semiconductor substrate; a first transistor set positioned in the first semiconductor substrate; a first dielectric layer covering a gate electrode of the first transistor set; a first interconnect member positioned in the first dielectric layer and electrically connected to the first transistor set; a second semiconductor substrate; a second transistor set positioned in the second semiconductor substrate and structurally different from the first transistor set; a second dielectric layer connected to the first dielectric layer, positioned between the first dielectric layer and the second semiconductor substrate, and covering a gate electrode of the second transistor set; and a second interconnect member positioned in the second dielectric layer, electrically connected to a terminal of the second transistor set, and electrically connected to the first interconnect member.