A method for processing semiconductor wafers includes obtaining measurement data from a surface of a semiconductor wafer processed by a front-end process tool. The method includes determining a center plane of the wafer based on the measurement data, generating raw shape profiles, and generating ideal shape profiles. The method further includes generating Gapi profiles based on the raw shape profiles and the ideal shape profiles, and calculating a Gapi value of the semiconductor wafer based on the Gapi profiles. The generated Gapi profiles and/or the calculated Gapi value may be used to tune the front-end process tool and/or sort the semiconductor wafer for polishing. Systems include at least a front-end process tool, a flatness measurement tool, and a computing device.

The embodiments of the present disclosure provide a display substrate, a display device, and a detection method for the display substrate. The display substrate includes: a base substrate including a display region and a peripheral region located on at least one side of the display region; a crack stopper located in the peripheral region and configured to prevent a crack from propagating toward the display region; an encapsulation structure disposed on the base substrate and covering the display region; and a crack detection structure disposed on the base substrate, wherein the crack detection structure is located on a side of the crack stopper facing the display region, an orthographic projection of the crack detection structure on the base substrate falls within an orthographic projection of the encapsulation structure on the base substrate, and the crack detection structure is configured to detect whether a crack exists in the encapsulation structure.

A processing condition specifying method that includes Steps S31, S32, and S33. In Step S31, a prediction thickness information piece containing prediction values of thicknesses after processing on the substrate W is calculated for each of a plurality of recipe information pieces based on measurement thickness information containing measurement values of thicknesses of the substrate W. In Step S32, the prediction thickness information pieces each calculated for a corresponding one of the recipe information pieces are evaluated according to a prescribed evaluation method and a prediction thickness information piece is selected from among the prediction thickness information pieces. In Step S33, a recipe information piece corresponding to the selected prediction thickness information piece is specified. The measurement values contained in the measurement thickness information indicate a thickness of the substrate W measured before processing on the substrate W.

Methods, systems, and computer programs are presented for predicting the performance of semiconductor manufacturing equipment operations. One method includes an operation for obtaining machine-learning (ML) models, each model related to predicting a performance metric for an operation of a semiconductor manufacturing tool. Further, each ML model utilizes features defining inputs for the ML model. The method further includes an operation for receiving a process definition for manufacturing a product with the semiconductor manufacturing tool. One or more ML models are utilized to estimate a performance of the process definition used in the semiconductor manufacturing tool. Additionally, the method includes presenting, on a display, results showing the estimate of the performance of the manufacturing of the product. In some aspects, the use of hybrid models improves the predictive accuracy of the system by augmenting the capabilities of data-driven models with the reinforcement provided by the physics-based models.

A method for processing semiconductor wafers includes obtaining measurement data of an edge profile of a semiconductor wafer processed by a front-end process tool. The method includes determining an edge profile center point based on the measurement data, generating a raw height profile, and generating an ideal edge profile. The method further includes generating a Gapi edge profile of the semiconductor wafer based on the raw height profile and the ideal edge profile and calculating a Gapi edge value of the semiconductor wafer based on the Gapi edge profile. The generated Gapi edge profile and/or the calculated Gapi edge value may be used to tune the front-end process tool and/or sort the semiconductor wafer for polishing. Systems include at least a front-end process tool, a flatness measurement tool, and a computing device.

A semiconductor process system includes a process chamber with a lid. The system includes a heater positioned on the lid and a controller configured to control the heater. The controller operates the heater to provide a selected temperature distribution of the lid.

A method for manufacturing an electronic device is provided, the method includes: providing an inspection module to inspect a first area of the electronic device to obtain a first information and inspect a second area of the electronic device to obtain a second information; transmitting the first information and the second information to a processing system; comparing the first information and the second information to obtain a difference; and transmitting a correction information to a first process machine via a first interface system. When the difference is greater than or equal to -2 and less than or equal to 2, the first process machine is started to produce. An electronic device is also provided.

A method of forming a semiconductor device can comprise providing a first shift region in which to determine a first displacement. A second shift region may be provided in which to determine a second displacement. A unique electrically conductive structure may be formed comprising traces to account for the first displacement and the second displacement. The electrically conductive structure may comprise traces comprising a first portion within the first shift region and a second portion of traces in the second shift region laterally offset from the first portion of traces. A third portion of the traces may be provided in the routing area between the first shift region and the second shift region. A unique variable metal fill may be formed within the fill area. The variable metal fill may be electrically isolated from the unique electrically conductive structure.

Enhanced probe cards, for testing unpackaged semiconductor die including numerous discrete devices (e.g., LEDs), are described. The die includes anodes and cathodes for the LEDs. Via a single touchdown event, the probe card may simultaneously operate each of the LEDs. The LEDs' optical output is measured and the performance of the die is characterized. The probe card includes a conductive first contact and another contact that are fabricated from a conformal sheet or film. Upon the touchdown event, the first contact makes contact with each of the die's anodes and the other contact makes contact with each of the die's cathodes. The vertical and sheet resistance of the contacts are sufficient such that the voltage drop across the vertical dimension of the contacts is approximately an order of magnitude greater than the operating voltage of the LEDs and current-sharing between adjacent LEDs is limited by the sheet resistance.

The present disclosure provides a method for fabricating an integrated circuit (IC). The method includes receiving an IC layout having active regions, conductive contact features landing on the active regions, and a conductive via feature to be landing on a first subset of the conductive contact features and to be spaced from a second subset of the conductive contact features; evaluating a spatial parameter of the conductive via feature to the conductive contact features; and modifying the IC layout according to the spatial parameter such that the conductive via feature has a S-curved shape.