A method for manufacturing an electronic device is provided, the method includes: providing an inspection module to inspect a first area of the electronic device to obtain a first information and inspect a second area of the electronic device to obtain a second information; transmitting the first information and the second information to a processing system; comparing the first information and the second information to obtain a difference; and transmitting a correction information to a first process machine via a first interface system. When the difference is greater than or equal to -2 and less than or equal to 2, the first process machine is started to produce. An electronic device is also provided.

A semiconductor device of an embodiment includes a plurality of chip regions, each including a memory region in which a plurality of memory cells is arranged, and a kerf region disposed between the chip regions and surrounding each chip region. Paired marks are arranged in a vicinity of the memory region of one of the plurality of chip regions and in a common hierarchical layer in the kerf region, and the paired marks are disposed over upper and lower hierarchical layers.

A measurement pattern for monitoring overlay shift of bonded wafers includes a top wafer pattern and a bottom wafer pattern. The top wafer pattern includes a first portion with a width Wx1 measured along a first axis. The bottom wafer pattern includes a first part with a width Wx2 measured along the first axis, wherein the first portion of the top wafer pattern and the first part of the bottom wafer pattern are separated by a target distance Dx, and wherein the measurement pattern satisfies the following measurement formulas:

Tx>Dx−Sx;

Tx<Dx−Sx+Wx2;

Tx>Sx;

Tx<Dx−Sx+Wx1; wherein, Tx represents a searching distance for finding an end-point of the first portion or an end-point of the first part; and Sx represents an actual shifting amount of the first portion.

The present disclosure provides a latch-up test structure, including: a substrate of a first conductive type; a first well region of the first conductive type, located in the substrate of the first conductive type; a first doped region of the first conductive type, located in the first well region of the first conductive type; a first doped region of a second conductive type, located in the first well region of the first conductive type; and a second doped region of the first conductive type, a second doped region of the second conductive type, a third doped region of the first conductive type, and a third doped region of the second conductive type that are arranged at intervals in the substrate of the first conductive type.

The invention is a cost effective multisite parallel wafer tester that has an array of stationary wafer test sites; a single mobile wafer handling and alignment carriage that holds a wafer handling robot, a wafer rotation pre-alignment assembly, a wafer alignment assembly, a wafer front opening unified pod (FOUP), and a wafer camera assembly; and a robot that moves the wafer handling and alignment carriage to and from each test site. Each test site contains a wafer probe card assembly and a floating chuck. In use, wafers are loaded from a front opening FOUP into a wafer buffer FOUP from which wafers are retrieved by the wafer handling and alignment assembly. The robot positions the wafer handling and alignment carriage and the associated wafer handling robot, the wafer rotation pre-alignment assembly, the wafer alignment assembly, the wafer FOUP, and the wafer camera assembly in front of and inside a given test site and aligns the wafer to be tested with the probe card inside the test site using the floating chuck.

The present disclosure provides a semiconductor manufacturing process control method and apparatus, a device, and a storage medium. The method includes: analyzing wafer lot information and determining a current product lot of a current product; obtaining historical measurement data within a specified period; when determining that the historical measurement data does not include first measurement data of the current product lot, if determining, based on preset configuration information, that the historical measurement data includes second measurement data of a target product lot, determining a target regulatory data based on the preset configuration information and the second measurement data; and controlling a production parameter of the current product based on the target regulatory data.

The present disclosure relates to a measurement mark, a semiconductor structure, a measurement method and device, and a storage medium. The measurement mark is provided on a semiconductor structure, the semiconductor structure including a substrate. The measurement mark is applied to an after etching inspection process. The measurement mark includes a first mark layer and a second mark layer, the first mark layer and the second mark layer being stacked. A projection contour of the first mark layer on the substrate coincides with a projection contour of the second mark layer on the substrate. The measurement mark includes a first mark group located on the first mark layer and a second mark group located on the second mark layer.

The present disclosure provides a semiconductor structure having a test structure. The semiconductor structure includes a semiconductor substrate, a memory device and a test structure. The memory device is disposed on the semiconductor substrate, and includes a device area and an edge area. The edge area surrounds the device area. The test structure is disposed on the semiconductor substrate, and includes a dummy area, a test edge area and a plurality of unit cells. The test edge area surrounds the dummy area. The plurality of unit cells are disposed in the test edge area, and the dummy area is free of the unit cells. A dimension of the test edge area in a top view is different from a dimension of the edge area in the top view.

A semiconductor wafer includes a semiconductor chip that includes a photonic device. The semiconductor chip includes an optical fiber attachment region in which an optical fiber alignment structure is to be fabricated. The optical fiber alignment structure is not yet fabricated in the optical fiber attachment region. The semiconductor chip includes an in-plane fiber-to-chip optical coupler positioned at an edge of the optical fiber attachment region. The in-plane fiber-to-chip optical coupler is optically connected to the photonic device. A sacrificial optical structure is optically coupled to the in-plane fiber-to-chip optical coupler. The sacrificial optical structure includes an out-of-plane optical coupler configured to receive input light from a light source external to the semiconductor chip. At least a portion of the sacrificial optical structure extends through the optical fiber attachment region.

A substrate drying device is provided that can suppress occurrence of a micro size defect (for example, a defect having a defect size of 20 nm or less). A substrate drying device 1 includes a substrate holding unit 11 which holds a substrate W, a gas generator 60 which generates a drying gas G including at least IPA vapor and for drying the substrate W, and a drying gas nozzle 30 which supplies the drying gas G to the surface WA of the substrate W. A filter 67 for filtering the drying gas G is provided in the gas generator 60. A defect size D allowed in a defect test after the drying of the substrate W is set to 20 nm or less and a ratio D/F of the defect size D and a filter size F of the filter 67 is set to 4 or more.