A voltage-reference plane has gradient regions that provide altered thicknesses that are useful in a power-deliver network for a semiconductor package substrate. Different signal trace types are located over various portions of the gradient regions to facilitate signal integrity.

A tuning structure to mitigate a capacitive discontinuity in an integrated circuit (IC) package includes an electrical conductor having a first end, a second end, and a conductor body between the first end and the second end. The first end is electrically coupled to a signal via, and the second end electrically coupled to an IC package core via cap. The electrical conductor is disposed substantially coplanar with the core via cap, and the conductor body is disposed along an outer perimeter of the core via cap. The second end is coupled to the via cap at a contact location. The contact location is determined based on a measurement of a performance metric associated with the transmission path through the IC package core, the core via cap, the electrical conductor, and the signal via.

Embodiments disclosed herein include electronic packages with improved differential signaling architectures. In an embodiment, the electronic package comprises a package substrate, where the package substrate comprises alternating metal layers and dielectric layers. In an embodiment, a first trace is embedded in the package substrate, where the first trace has a first thickness that extends from a first metal layer to a second metal layer. In an embodiment, the electronic package further comprises a first ground plane laterally adjacent to a first side of the first trace, and a second ground plane laterally adjacent to a second side of the first trace.

An electronic device package is described. The electronic device package includes one or more dies. The electronic device package includes an interposer coupled to the one or more dies. The electronic device package also includes a package substrate coupled to the interposer. The electronic device package includes a plurality of through-silicon vias (TSVs) in at least one die of the one or more dies, or the interposer, or both. The electronic device package includes a passive equalizer structure communicatively coupled to a TSV pair in the plurality of TSVs. The passive equalizer structure is operable to minimize a level of insertion loss variation in the TSV pair.

A package device comprises a first transceiver comprising a first integrated circuit (IC) die and transmitter circuitry, and a second transceiver comprising a second IC die and receiver circuitry. The receiver circuitry is coupled to the transmitter circuitry via a channel. The package device further comprises an interconnection device connected to the first IC die and the second IC die. The interconnection device comprises a channel connecting the transmitter circuitry with the receiver circuitry, and a passive inductive element disposed external to the first IC die and the second IC die and along the channel.

A first frame includes portions of a first short side surface and a first long side surface, in which a plurality of conductor layers to which a plurality of DC electrode terminals are connected, and a plurality of insulating layers arranged between the plurality of conductor layers are stacked. Further, a second frame includes portions of a second short side surface and a second long side surface.

After a distal end portion of a first lead of a first lead frame is connected to a first signal pad, and a distal end portion of a second lead is connected to a second signal pad, the interval between the linear portion of the first lead and the linear portion of the second lead is adjusted using a lead shape changing jig.

A wiring base includes an insulation base having a first surface, a first differential-wiring channel, and a second differential-wiring channel. The first and the second differential-wiring channels are on the first surface and arranged side by side in a first direction. The first differential-wiring channel includes a pair of first signal conductors extending in a second direction intersecting the first direction and a pair of first grounding conductors extending along the first signal conductors with the first signal conductors being interposed therebetween. The second differential-wiring channel includes a pair of second signal conductors extending in the second direction and a pair of second grounding conductors extending along the second signal conductors with the second signal conductors being interposed therebetween. The wiring base further includes a first film extending in the second direction and positioned between first and second grounding conductors adjacent to each other in plan of the first surface.

An optical module includes an optical semiconductor chip including a first electrode pad, a second electrode pad, and a third electrode pad arranged between the first electrode pad and the second electrode pad, a wiring substrate on which the optical semiconductor chip is flip-chip mounted, including a fourth electrode pad, a fifth electrode pad, and a sixth electrode pad arranged between the fourth electrode pad and the fifth electrode pad, a first conductive material connecting the first electrode pad with the fourth electrode pad, a second conductive material connecting the second electrode pad with the fifth electrode pad, a third conductive material arranged between the first conductive material and the second conductive material, connecting the third electrode pad with the sixth electrode pad, and a resin provided in an area on the second conductive material side of the third conductive material between the optical semiconductor chip and the wiring substrate.

Provided is a semiconductor package including a pair of differential signal wiring lines including a first differential signal wiring line and a second differential signal wiring line, extending parallel to and spaced apart from each other, a lower equal potential plate in a lower wiring layer under the signal wiring layer, an upper equal potential plate in an upper wiring layer above the signal wiring layer, and a wiring insulating layer adjacent to the pair of differential signal wiring lines, the lower equal potential plate, and the upper equal potential plate, the wiring insulating layer filling spaces between the signal wiring layer, the lower wiring layer, and the upper wiring layer, at least one of the lower equal potential plate and the upper equal potential plate including an impedance opening overlapping the pair of differential signal wiring lines in a vertical direction and is filled by the wiring insulating layer.