Power control and decoupling capacitance arrangements for integrated circuit devices are discussed herein. In one example, an assembly includes a first circuit assembly comprising a first circuit board coupled to an integrated circuit device, wherein the first circuit board is coupled to first surface of a system circuit board. The assembly also includes a second circuit assembly comprising a second circuit board having one or more voltage adjustment units configured to supply at least one input voltage to the integrated circuit device, wherein the second circuit board is coupled to a second surface of the system circuit board and positioned at least partially under a footprint of the integrated circuit device with respect to the system circuit board.

A number of monolithic diode limiter semiconductor structures are described. The diode limiters can include a hybrid arrangement of diodes with different intrinsic regions, all formed over the same semiconductor substrate. In one example, a method of manufacture of a monolithic diode limiter includes providing an N-type semiconductor substrate, providing an intrinsic layer on the N-type semiconductor substrate, implanting a first P-type region to a first depth into the intrinsic layer, implanting a second P-type region to a second depth into the intrinsic layer, and forming at least one passive circuit element over the intrinsic layer. The method can also include forming an insulating layer on the intrinsic layer, forming a first opening in the insulating layer, and forming a second opening in the insulating layer. The method can also include implanting the first P-type region through the first opening and implanting the second P-type region through the second opening.

A semiconductor device package includes a plurality of input leads and an output lead, a plurality of transistor amplifier dies having inputs respectively coupled to the plurality of input leads, and a combination circuit configured to combine output signals received from the plurality of transistor amplifier dies and output a combined signal to the output lead.

The present disclosure relates to an electronic device with an integral filtering component. The electronic device includes a semiconductor component, an insulating layer, at least one contact plug, and a filtering component. The insulating layer is disposed on the semiconductor component. The contact plug penetrates through the insulating layer. The filtering component is disposed on the insulating layer and the contact plug. The filtering component includes a bottom electrode, an isolation layer, a top electrode, and a dielectric layer. The bottom electrode is divided into a first segment connected to the contact plug and a second segment separated from the first segment. The isolation layer is disposed on the bottom electrode, the top electrode is disposed in the isolation layer, and the dielectric layer is disposed between the bottom electrode and the top electrode.

In various embodiments, a bonded structure is disclosed. The bonded structure can include an element and a passive electronic component having a first surface bonded to the element and a second surface opposite the first surface. The passive electronic component can comprise a first anode terminal bonded to a corresponding second anode terminal of the element and a first cathode terminal bonded to a corresponding second cathode terminal of the element. The first anode terminal and the first cathode terminal can be disposed on the first surface of the passive electronic component.

A semiconductor package includes a mounting platform including an electrically insulating substrate and structured metallization layers, a semiconductor die mounted on an upper surface of the mounting platform, the semiconductor die including a first terminal and a second terminal, the first terminal disposed on a second surface of the semiconductor die that faces the mounting platform, the second terminal disposed on a first surface of the semiconductor die that faces away from the mounting platform, and a heat sink integrally formed in the mounting platform. The heat sink is directly underneath the semiconductor die and is thermally coupled to the semiconductor die. The heat sink extends from the upper surface of the mounting platform to a lower surface of the mounting platform. The heat sink includes one or more discrete metal blocks disposed within an opening formed in the electrically insulating substrate.

A high-frequency circuit device includes: a chip which includes a high-frequency element, a high-frequency circuit, a signal conductor, and a chip ground; a package substrate on which the chip is disposed, a shunt path which is constituted by a package signal conductor which is disposed on an upper surface of the package substrate and is electrically connected to the signal conductor, a package first ground which is electrically connected to the chip ground, and a shunt element which is electrically connected to the package signal conductor and the package first ground; and a package second ground which is disposed at least inside the base of the package substrate or on a back surface of the package substrate, wherein a part of the base, a part of the shunt path, and the package second ground constitute a capacitive structure.

A method reduces an area of a mounting electrode provided on a first surface of a multilayer body and connected to a specific component is reduced and decreases a pitch between mounting electrodes. A plating film is formed on the mounting electrodes with the reduced area. The mounting electrodes for connection to specific components are defined by first end surfaces of first via conductors, and hence, the areas of the mounting electrodes are significantly reduced, and the pitch between the mounting electrodes is significantly decreased. Also, the mounting electrodes defined by the first end surfaces of the first via conductors are connected to plane electrodes at end surfaces of second via conductors exposed from a surface of the multilayer body with internal wiring electrodes interposed therebetween. Thus, a plating film is able to be reliably provided on the mounting electrodes.

A package substrate is disclosed. The package substrate includes a die package in the package substrate located at least partially underneath a location of a power delivery interface in a die that is coupled to the surface of the package substrate. Connection terminals are accessible on a surface of the die package to provide connection to the die that is coupled to the surface of the package substrate. Metal-insulator-metal layers inside the die package are coupled to the connection terminals.

An embodiment of a radio-frequency (RF) device includes at least one transistor, a package, and a surface-mountable capacitor. The package contains the at least one transistor and includes at least one termination. The surface-mountable capacitor is coupled in a shunt configuration between the at least one transistor and a power supply terminal of the device to decouple the at least one transistor from a power supply.