A semiconductor device has an electronic component assembly with a substrate and a plurality of electrical components disposed over the substrate. A conductive post is formed over the substrate. A molding compound sheet is disposed over the electrical component assembly. A carrier including a first electrical circuit pattern is disposed over the molding compound sheet. The carrier is pressed against the molding compound sheet to dispose a first encapsulant over and around the electrical component assembly and embed the first electrical circuit pattern in the first encapsulant. A shielding layer can be formed over the electrical components assembly. The carrier is removed to expose the first electrical circuit pattern. A second encapsulant is deposited over the first encapsulant and the first electrical circuit pattern. A second electrical circuit pattern is formed over the second encapsulant. A semiconductor package is disposed over the first electrical circuit pattern.

A semiconductor device has an electronic component assembly with a substrate and a plurality of electrical components disposed over the substrate. A conductive post is formed over the substrate. A molding compound sheet is disposed over the electrical component assembly. A carrier including a first electrical circuit pattern is disposed over the molding compound sheet. The carrier is pressed against the molding compound sheet to dispose a first encapsulant over and around the electrical component assembly and embed the first electrical circuit pattern in the first encapsulant. A shielding layer can be formed over the electrical components assembly. The carrier is removed to expose the first electrical circuit pattern. A second encapsulant is deposited over the first encapsulant and the first electrical circuit pattern. A second electrical circuit pattern is formed over the second encapsulant. A semiconductor package is disposed over the first electrical circuit pattern.

A semiconductor device with redistribution layers formed utilizing dummy substrates is disclosed and may include forming a first redistribution layer on a first dummy substrate, forming a second redistribution layer on a second dummy substrate, electrically connecting a semiconductor die to the first redistribution layer, electrically connecting the first redistribution layer to the second redistribution layer, and removing the dummy substrates. The first redistribution layer may be electrically connected to the second redistribution layer utilizing a conductive pillar. An encapsulant material may be formed between the first and second redistribution layers. Side portions of one of the first and second redistribution layers may be covered with encapsulant. A surface of the semiconductor die may be in contact with the second redistribution layer. The dummy substrates may be in panel form. One of the dummy substrates may be in panel form and the other in unit form.

A semiconductor device has an electronic component assembly with a substrate and a plurality of electrical components disposed over the substrate. A conductive post is formed over the substrate. A molding compound sheet is disposed over the electrical component assembly. A carrier including a first electrical circuit pattern is disposed over the molding compound sheet. The carrier is pressed against the molding compound sheet to dispose a first encapsulant over and around the electrical component assembly and embed the first electrical circuit pattern in the first encapsulant. A shielding layer can be formed over the electrical components assembly. The carrier is removed to expose the first electrical circuit pattern. A second encapsulant is deposited over the first encapsulant and the first electrical circuit pattern. A second electrical circuit pattern is formed over the second encapsulant. A semiconductor package is disposed over the first electrical circuit pattern.

Reduced-profile semiconductor device apparatus are achieved by thinning a semiconductive device substrate at a backside surface to expose a through-silicon via pillar, forming a recess to further expose the through-silicon via pillar, and by seating an electrical bump in the recess to contact both the through-silicon via pillar and the recess. In an embodiment, the electrical bump contacts a semiconductor package substrate to form a low-profile semiconductor device apparatus. In an embodiment, the electrical bump contacts a subsequent die to form a low-profile semiconductor device apparatus.

Reduced-profile semiconductor device apparatus are achieved by thinning a semiconductive device substrate at a backside surface to expose a through-silicon via pillar, forming a recess to further expose the through-silicon via pillar, and by seating an electrical bump in the recess to contact both the through-silicon via pillar and the recess. In an embodiment, the electrical bump contacts a semiconductor package substrate to form a low-profile semiconductor device apparatus. In an embodiment, the electrical bump contacts a subsequent die to form a low-profile semiconductor device apparatus.

A semiconductor device with redistribution layers formed utilizing dummy substrates is disclosed and may include forming a first redistribution layer on a first dummy substrate, forming a second redistribution layer on a second dummy substrate, electrically connecting a semiconductor die to the first redistribution layer, electrically connecting the first redistribution layer to the second redistribution layer, and removing the dummy substrates. The first redistribution layer may be electrically connected to the second redistribution layer utilizing a conductive pillar. An encapsulant material may be formed between the first and second redistribution layers. Side portions of one of the first and second redistribution layers may be covered with encapsulant. A surface of the semiconductor die may be in contact with the second redistribution layer. The dummy substrates may be in panel form. One of the dummy substrates may be in panel form and the other in unit form.

A package includes a chip, a wire, a mold layer and a redistribution layer. The chip includes a conductive pad. The wire is bonded to the conductive pad of the chip. The mold layer surrounds the first chip and the wire. The redistribution layer is disposed on the mold layer and contacts an exposed portion of the wire.

CTE compensation for wafer-level and chip-scale packages and assemblies.

A microelectronic package includes at least one microelectronic element having a front surface defining a plane, the plane of each microelectronic element parallel to the plane of any other microelectronic element. An encapsulation region overlying edge surfaces of each microelectronic element has first and second major surfaces substantially parallel to the plane of each microelectronic element and peripheral surfaces between the major surfaces. Wire bonds are electrically coupled with one or more first package contacts at the first major surface of the encapsulation region, each wire bond having a portion contacted and surrounded by the encapsulation region. Second package contacts at an interconnect surface being one or more of the second major surface and the peripheral surfaces include portions of the wire bonds at such surface, and/or electrically conductive structure electrically coupled with the wire bonds.