A power semiconductor chip having: a semiconductor component body; a multilayer metallization arranged on the semiconductor component body; and a nickel layer arranged over the semiconductor component body. The invention further relates to a method for producing a power semiconductor chip and to a power semiconductor device. The invention provides a power semiconductor chip which has a metallization to which a copper wire, provided without a thick metallic coating, can be reliably bonded without damage to the power semiconductor chip during bonding.

A system and method for bonding an electrically conductive mechanical interconnector (e.g., a bonding wire, solder, etc.) to an electrical contact (e.g., contact pad, termination on a printed circuit board (PCB), etc.) made from an electrically conductive metal (e.g., aluminum) on an electronic device (e.g., integrated circuit (IC), die, wafer, PCB, etc.) is provided. The electrical contact is chemically coated with a metal (e.g., cobalt) that provides a protective barrier between the mechanical interconnector and the electrical contact. The protective barrier provides a diffusion barrier to inhibit galvanic corrosion (i.e. ion diffusion) between the mechanical interconnector and the electrical contact.

A power semiconductor chip having: a semiconductor component body; a multilayer metallization arranged on the semiconductor component body; and a nickel layer arranged over the semiconductor component body. The invention further relates to a method for producing a power semiconductor chip and to a power semiconductor device. The invention provides a power semiconductor chip which has a metallization to which a copper wire, provided without a thick metallic coating, can be reliably bonded without damage to the power semiconductor chip during bonding.

A system and method for bonding an electrically conductive mechanical interconnector (e.g., a bonding wire, solder, etc.) to an electrical contact (e.g., contact pad, termination on a printed circuit board (PCB), etc.) made from an electrically conductive metal (e.g., aluminum) on an electronic device (e.g., integrated circuit (IC), die, wafer, PCB, etc.) is provided. The electrical contact is chemically coated with a metal (e.g., cobalt) that provides a protective barrier between the mechanical interconnector and the electrical contact. The protective barrier provides a diffusion barrier to inhibit galvanic corrosion (i.e. ion diffusion) between the mechanical interconnector and the electrical contact.

A fluxless bonding process is provided. An array of micro solder bumps of a first semiconductor structure is aligned to an array of bonding pads of a second semiconductor structure under an applied bonding force. An environment is provided to prevent oxides from forming on the solder bump structures and bonding pads during the bonding process. A scrubbing process is performed at a given scrubbing frequency and amplitude to scrub the micro solder bumps against the bonding pads in a direction perpendicular to the bonding. Heat is applied to at least the first semiconductor structure to melt and bond the micro solder bumps to the bonding pads. The first semiconductor structure is cooled down to solidify the molten solder. Coplanarity is maintained between the bonding surfaces of the semiconductor structures within a given tolerance during the scrubbing and cooling steps until solidification of the micro solder bumps.

A fluxless bonding process is provided. An array of micro solder bumps of a first semiconductor structure is aligned to an array of bonding pads of a second semiconductor structure under an applied bonding force. An environment is provided to prevent oxides from forming on the solder bump structures and bonding pads during the bonding process. A scrubbing process is performed at a given scrubbing frequency and amplitude to scrub the micro solder bumps against the bonding pads in a direction perpendicular to the bonding. Heat is applied to at least the first semiconductor structure to melt and bond the micro solder bumps to the bonding pads. The first semiconductor structure is cooled down to solidify the molten solder. Coplanarity is maintained between the bonding surfaces of the semiconductor structures within a given tolerance during the scrubbing and cooling steps until solidification of the micro solder bumps.

A 3D interconnect structure and method of manufacture are described in which metal redistribution layers (RDLs) are integrated with through-silicon vias (TSVs) and using a plate through resist type process flow. A silicon nitride or silicon carbide passivation layer may be provided between the thinned device wafer back side and the RDLs to provide a hermetic barrier and polish stop layer during the process flow.

A 3D interconnect structure and method of manufacture are described in which metal redistribution layers (RDLs) are integrated with through-silicon vias (TSVs) and using a plate through resist type process flow. A silicon nitride or silicon carbide passivation layer may be provided between the thinned device wafer back side and the RDLs to provide a hermetic barrier and polish stop layer during the process flow.

A fluxless bonding process is provided. An array of micro solder bumps of a first semiconductor structure is aligned to an array of bonding pads of a second semiconductor structure under an applied bonding force. An environment is provided to prevent oxides from forming on the solder bump structures and bonding pads during the bonding process. A scrubbing process is performed at a given scrubbing frequency and amplitude to scrub the micro solder bumps against the bonding pads in a direction perpendicular to the bonding. Heat is applied to at least the first semiconductor structure to melt and bond the micro solder bumps to the bonding pads. The first semiconductor structure is cooled down to solidify the molten solder. Coplanarity is maintained between the bonding surfaces of the semiconductor structures within a given tolerance during the scrubbing and cooling steps until solidification of the micro solder bumps.

A fluxless bonding process is provided. An array of micro solder bumps of a first semiconductor structure is aligned to an array of bonding pads of a second semiconductor structure under an applied bonding force. An environment is provided to prevent oxides from forming on the solder bump structures and bonding pads during the bonding process. A scrubbing process is performed at a given scrubbing frequency and amplitude to scrub the micro solder bumps against the bonding pads in a direction perpendicular to the bonding. Heat is applied to at least the first semiconductor structure to melt and bond the micro solder bumps to the bonding pads. The first semiconductor structure is cooled down to solidify the molten solder. Coplanarity is maintained between the bonding surfaces of the semiconductor structures within a given tolerance during the scrubbing and cooling steps until solidification of the micro solder bumps.