A display device includes a substrate including a pad area, a first conductive pattern disposed in the pad area on the substrate, an insulating layer disposed on the first conductive pattern and overlapping the first conductive pattern, second conductive patterns disposed on the insulating layer, spaced apart from each other, and contacting the first conductive pattern through contact holes formed in the insulating layer, and a third conductive pattern disposed on the second conductive patterns and contacting the insulating layer.

A semiconductor device includes a semiconductor substrate including a circuit layer disposed therein, a bonding pad disposed on the semiconductor substrate, the bonding pad being electrically connected to the circuit layer, and a metal layer electrically connected to the bonding pad. The metal layer includes a first via electrically connected to the bonding pad, the first via providing an electrical path between the metal layer and the circuit layer, and a second via protruding toward the semiconductor substrate, the second via supporting the metal layer on the semiconductor substrate.

A display device includes a substrate including an active area having pixels and a non-active area including a pad region. A pad electrode is disposed in the pad region and includes a first pad electrode and a second pad electrode disposed on the first pad electrode. A first insulating pattern is interposed between the first and second pad electrodes. In a plan view, the first insulating pattern is positioned inside the first pad electrode, and a portion of the second pad electrode overlapping the first insulating pattern protrudes further from the substrate in a thickness direction than a portion of the second pad electrode not overlapping the first insulating pattern. The second pad electrode directly contacts a portion of the upper surface of the first pad electrode. In a plan view, an area of the second pad electrode is greater than an area of the first pad electrode.

A semiconductor device assembly includes a substrate and a die coupled to the substrate, the die including a first contact pad electrically coupled to a first circuit on the die including an active circuit element, a first TSV electrically coupling the first contact pad to a first backside contact pad, and a second contact pad electrically coupled to a second circuit including only passive circuit elements. The substrate includes a substrate contact electrically coupled to the first and second contact pads. The assembly can further include a second die including a third contact pad electrically coupled to a third circuit including a second active circuit element, and a fourth contact pad electrically coupled to a fourth circuit on the second die including only passive circuit elements. The substrate contact can be electrically coupled to the third contact pad, but electrically disconnected from the fourth contact pad.

A semiconductor layer includes an opening, and in a joint surface between structures, a portion between a semiconductor layer and an opening in a direction in which the semiconductor layers are stacked together includes a plurality of conductor portions and an insulator portion located between the plurality of conductor portions in a direction orthogonal to the direction.

A semiconductor chip includes a semiconductor substrate having a main surface, first and second electrodes, a first insulating layer, and first and second bumps. The first and second electrodes are formed above the main surface of the semiconductor substrate. The first insulating layer is formed above a first portion of the first electrode. The first bump is formed above a second portion of the first electrode and above the first insulating layer and is electrically connected to the first electrode. The second bump is formed above the second electrode. The area of the second bump is larger than that of the first bump in a plan view of the main surface of the semiconductor substrate. The first insulating layer adjusts the distance from the main surface of the semiconductor substrate to the top surface of the first bump in a direction normal to the main surface.

A semiconductor device assembly includes a substrate and a die coupled to the substrate, the die including a first contact pad electrically coupled to a first circuit on the die including an active circuit element, a first TSV electrically coupling the first contact pad to a first backside contact pad, and a second contact pad electrically coupled to a second circuit including only passive circuit elements. The substrate includes a substrate contact electrically coupled to the first and second contact pads. The assembly can further include a second die including a third contact pad electrically coupled to a third circuit including a second active circuit element, and a fourth contact pad electrically coupled to a fourth circuit on the second die including only passive circuit elements. The substrate contact can be electrically coupled to the third contact pad, but electrically disconnected from the fourth contact pad.

A display device includes a substrate including an active area having pixels and a non-active area including a pad region. A pad electrode is disposed in the pad region and includes a first pad electrode and a second pad electrode disposed on the first pad electrode. A first insulating pattern is interposed between the first and second pad electrodes. In a plan view, the first insulating pattern is positioned inside the first pad electrode, and a portion of the second pad electrode overlapping the first insulating pattern protrudes further from the substrate in a thickness direction than a portion of the second pad electrode not overlapping the first insulating pattern. The second pad electrode directly contacts a portion of the upper surface of the first pad electrode. In a plan view, an area of the second pad electrode is greater than an area of the first pad electrode.

A semiconductor device assembly includes a substrate and a die coupled to the substrate, the die including a first contact pad electrically coupled to a first circuit on the die including an active circuit element, a first TSV electrically coupling the first contact pad to a first backside contact pad, and a second contact pad electrically coupled to a second circuit including only passive circuit elements. The substrate includes a substrate contact electrically coupled to the first and second contact pads. The assembly can further include a second die including a third contact pad electrically coupled to a third circuit including a second active circuit element, and a fourth contact pad electrically coupled to a fourth circuit on the second die including only passive circuit elements. The substrate contact can be electrically coupled to the third contact pad, but electrically disconnected from the fourth contact pad.

A chip package including a substrate having an upper surface, a lower surface, and a sidewall surface that is at the edge of the substrate is provided. The substrate includes a sensor device therein and adjacent to the upper surface thereof. The chip package further includes light-shielding layer disposed over the sidewall surface of the substrate and extends along the edge of the substrate to surround the sensor device. The chip package further includes a cover plate disposed over the upper surface of the substrate and a spacer layer disposed between the substrate and the cover plate. A method of forming the chip package is also provided.