A semiconductor package includes a semiconductor chip, a lower redistribution layer disposed under the semiconductor chip, the lower redistribution layer including a plurality of lower insulating layers, a plurality of lower redistribution patterns, and a plurality of lower conductive vias, a lower passivation layer disposed under the lower redistribution layer and provided with a recess at a bottom surface of the lower passivation layer, an under bump metallization (UBM) pad disposed in the first recess, a UBM protective layer disposed in the first recess and connected to the lower conductive vias while covering a top surface and opposite side surfaces of the UBM pad, and an outer connecting terminal connected to a bottom surface of the UBM pad. The bottom surface of the UBM pad is positioned at a first depth from the bottom surface of the lower passivation layer.

A power semiconductor chip having: a semiconductor component body; a multilayer metallization arranged on the semiconductor component body; and a nickel layer arranged over the semiconductor component body. The invention further relates to a method for producing a power semiconductor chip and to a power semiconductor device. The invention provides a power semiconductor chip which has a metallization to which a copper wire, provided without a thick metallic coating, can be reliably bonded without damage to the power semiconductor chip during bonding.

A semiconductor package structure is provided. The semiconductor package structure includes a substrate, a semiconductor die, a molding material, a first bonding layer, and a thermal interface material. The semiconductor die is disposed over the substrate. The molding material surrounds the semiconductor die. The first bonding layer is disposed over the semiconductor die. The thermal interface material is disposed over the molding material.

A semiconductor package structure is provided. The semiconductor package structure includes a substrate, a semiconductor die, a molding material, a first bonding layer, and a thermal interface material. The semiconductor die is disposed over the substrate. The molding material surrounds the semiconductor die. The first bonding layer is disposed over the semiconductor die. The thermal interface material is disposed over the molding material.

A three dimensional multi-die package includes a first die and second die. The first die includes a contact attached to solder. The second die is thinned by adhesively attaching a handler to a top side of the second die and thinning a bottom side of the second die. The second die includes a multilayer contact of layered metallurgy that inhibits transfer of adhesive thereto. The layered metallurgy includes at least one layer that is wettable to the solder. The multilayer contact may include a Nickel layer, a Copper layer upon the Nickel layer, and a Nickel-Iron layer upon the Copper layer. The multilayer contact may also include a Nickel layer, a Copper-Tin layer upon the Nickel layer, and a Tin layer upon the Copper-Tin layer.

Contact bumps between a contact pad and a substrate can include a rough surface that can mate with the material of the substrate of which may be flexible. The rough surface can enhance the bonding strength of the contacts, for example, against shear and tension forces, especially for flexible systems such as smart label and may be formed via roller or other methods.

Contact bumps between a contact pad and a substrate can include a rough surface that can mate with the material of the substrate of which may be flexible. The rough surface can enhance the bonding strength of the contacts, for example, against shear and tension forces, especially for flexible systems such as smart label and may be formed via roller or other methods.

A power semiconductor device, a power semiconductor module and a power semiconductor device processing method are provided. The power semiconductor device includes a first load terminal structure, a second load terminal structure, and a semiconductor structure electrically coupled to each load terminal structure and configured to carry a load current. The first load terminal structure includes a conductive layer in contact with the semiconductor structure, a bonding block configured to be contacted by at least one bond wire and to receive at least a part of the load current from the at least one bond wire and/or the conductive layer, a support block having a hardness greater than the hardness of the conductive layer and the bonding block. The bonding block is mounted on the conductive layer via the support block, and a zone is arranged within the conductive layer and/or the bonding block, the zone exhibiting nitrogen atoms.

A power semiconductor device, a power semiconductor module and a power semiconductor device processing method are provided. The power semiconductor device includes a first load terminal structure, a second load terminal structure, and a semiconductor structure electrically coupled to each load terminal structure and configured to carry a load current. The first load terminal structure includes a conductive layer in contact with the semiconductor structure, a bonding block configured to be contacted by at least one bond wire and to receive at least a part of the load current from the at least one bond wire and/or the conductive layer, a support block having a hardness greater than the hardness of the conductive layer and the bonding block. The bonding block is mounted on the conductive layer via the support block, and a zone is arranged within the conductive layer and/or the bonding block, the zone exhibiting nitrogen atoms.

A semiconductor device according to the present disclosure includes a semiconductor substrate, a first electrode provided on the semiconductor substrate, an insulating layer including a first part provided on an upper surface of the first electrode, a second electrode including a main portion and an eaves portion, the main portion being provided on the upper surface of the first electrode, the eaves portion extending over the first part and solder covering an upper surface of the main portion and a part of an upper surface of the eaves portion wherein the insulating layer includes a second part covering a part of the upper surface of the eaves portion, the part being closer to an end portion of the eaves portion than the part covered by the solder and a third part connecting the first part and the second part and covering the end portion of the eaves portion.