Patent classifications
H
ELECTRICITY
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H01
ELECTRIC ELEMENTS
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H01L
SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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2224/00
Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
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H01L2224/01
Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
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H01L2224/02
Bonding areas; Manufacturing methods related thereto
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H01L2224/04
Structure, shape, material or disposition of the bonding areas prior to the connecting process
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H01L2224/06
of a plurality of bonding areas
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H01L2224/0614
Circular array, i.e. array with radial symmetry
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H01L2224/06144
covering only portions of the surface to be connected
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H01L2224/06146
Covering only the central area of the surface to be connected, i.e. central arrangements
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H01L2224/06146

SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD FOR FORMING THE SAME
20170098628 · 2017-04-06 ·

A semiconductor package structure is provided. The semiconductor package structure includes a semiconductor body and a conductive structure disposed below the semiconductor body. The semiconductor package structure also includes an insulating layer surrounding the conductive structure. The semiconductor package structure further includes a redistribution layer structure coupled to the conductive structure. In addition, the semiconductor package structure includes a molding compound surrounding the semiconductor body. A portion of the molding compound extends between the redistribution layer structure and the semiconductor body.