A display device comprises a display panel including a display area including pixels, and a pad area adjacent to the display area, and a driving integrated circuit mounted on the pad area, wherein the pad area includes a stud pad area located at an edge of the pad area and including at least one stud pad electrode, the driving integrated circuit includes a circuit base, and at least one stud bump area overlapping the stud pad area in a thickness direction of the display device and including at least one stud bump, and the at least one stud pad electrode overlaps an edge portion of the at least one stud bump.

Provided is an interposer for a semiconductor package, the interposer including an interposer substrate comprising a first main surface and a second main surface opposite to the first main surface, a first through-electrode structure and a second through-electrode structure each passing through the interposer substrate and protruding from the first main surface, a connection terminal structure contacting both the first through-electrode structure and the second through-electrode structure, and a photosensitive polymer layer arranged between the connection terminal structure and the interposer substrate, and between the first through-electrode structure and the second through-electrode structure.

An arrayed switch circuit includes a substrate, signal conductive pads and signal expansion pins. The signal conductive pads are disposed on the substrate at intervals, and the signal conductive pads are arranged to form a signal conductive pad array. Each of the signal conductive pads has a row position and a column position in the signal conductive pad array. A row signal switch is provided between any two adjacent signal conductive pads corresponding to the same row position, and a column signal switch is provided between any two adjacent signal conductive pads corresponding to the same column position. The signal expansion pins are connected to the signal conductive pads located on at least one side of the signal conductive pad array through signal expansion switches respectively.

Provided is an interposer for a semiconductor package, the interposer including an interposer substrate comprising a first main surface and a second main surface opposite to the first main surface, a first through-electrode structure and a second through-electrode structure each passing through the interposer substrate and protruding from the first main surface, a connection terminal structure contacting both the first through-electrode structure and the second through-electrode structure, and a photosensitive polymer layer arranged between the connection terminal structure and the interposer substrate, and between the first through-electrode structure and the second through-electrode structure.

Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface, and a die secured to the package substrate, wherein the die has a first surface and an opposing second surface, the die has first conductive contacts at the first surface and second conductive contacts at the second surface, and the first conductive contacts are coupled to conductive pathways in the package substrate by first non-solder interconnects.

Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface, and a die secured to the package substrate, wherein the die has a first surface and an opposing second surface, the die has first conductive contacts at the first surface and second conductive contacts at the second surface, and the first conductive contacts are coupled to conductive pathways in the package substrate by first non-solder interconnects.

According to one embodiment, a semiconductor device includes a first chip, and a second chip bonded to the first chip. The first chip includes: a substrate; a transistor provided on the substrate; a plurality of first wirings provided above the transistor; and a plurality of first pads provided above the first wirings. The second chip includes: a plurality of second pads coupled to the plurality of first pads, respectively; a plurality of second wirings provided above the second pads; and a memory cell array provided above the second wirings. The first wiring, the first pad, the second pad, and the second wiring are coupled to one another in series to form a first pattern.

A light emitting device includes a light emitting diode chip, a light transmitting member, a white barrier member, and a conductive adhesive member. The light emitting diode chip has a bump pad formed on the lower surface thereof. The light transmitting member covers the side surfaces and the upper surface of the light emitting diode chip, and the upper surface of the light transmitting member has a rectangular shape having long sides and short sides. The conductive adhesive member is formed to extend through the white barrier member from the bottom of the light emitting diode chip. The upper surface of the conductive adhesive member is connected to the bump pad of the light emitting diode chip, and the lower surface of the conductive adhesive member is exposed at the lower surface of the white barrier member.

Semiconductor devices are disclosed. According to some embodiments, a semiconductor device may include a memory array area and a peripheral area. The memory array area may include a number of memory cells and a number of array pads configured to receive an input voltage. The peripheral area may include a number of peripheral pads for interfacing with the memory array area. In these or other embodiments, the peripheral area may be arranged adjacent to a first edge of the semiconductor device and the number of array pads may be arranged proximate to a second edge of the semiconductor device. The second edge may be perpendicular to the first edge. The memory array area may also include an array distribution conductor configured to variously electrically connect the number of memory cells to the number of array pads. A semiconductor-device package and system are also disclosed.

Solid-state lighting devices including light-emitting diodes (LEDs) and more particularly LED chips with interconnect structures are disclosed. LED chips are provided that include first interconnects electrically coupled to an n-type layer and second interconnects electrically connected to a p-type layer. Configurations of the first and second interconnects are provided that may improve current spreading by reducing localized areas of current crowding within LED chips. Various configurations are disclosed that include collectively formed symmetric patterns of the first and second interconnects, diameters of certain ones of either the first or second interconnects that vary based on their relative positions in LED chips, and spacings of the second interconnects that vary based on their distances from the first interconnects. In this regard, LED chips are disclosed with improved current spreading as well as higher lumen outputs and efficiencies.