A method for manufacturing electronic chips includes forming, on the side of a first face of a semiconductor substrate, in and on which a plurality of integrated circuits has been formed beforehand, metallizations coupling contacts of adjacent integrated circuits to one another. The method further includes forming, on the side of the first face of the substrate, first trenches extending through the first face of the substrate and laterally separating the adjacent integrated circuits. The first trenches extend through the metallizations to form at least a portion of metallizations at each of the adjacent circuits.

For example, a semiconductor device includes one or more first subcontacts electrically conducted to a substrate. At least one of the one or more first subcontacts is formed in an element arrangement region, and has a lower impedance than the substrate. Preferably, at least one of the one or more first subcontacts is adjacent to a circuit element formed in the element arrangement region. Preferably, on the substrate, which is of a first conductivity type, an epilayer of a second conductivity type is formed, and the one or more first subcontacts include a first line having a lower impedance than the substrate, and a semiconductor region of the first conductivity type penetrating through the epilayer to electrically conduct the first line and the substrate to each other.

An array substrate has a display area and a bonding area located on a side of the display area. The array substrate includes a base, a plurality of first transistors, a plurality of conductive pins and a plurality of conductive electrodes. The plurality of first transistors are disposed on a side of the base and located in the display area; a first transistor includes a first gate, a first source and a first drain. The plurality of conductive pins are disposed on the side of the base and located in the bonding area, and are disposed in a same layer as the first gate. The plurality of conductive electrodes are each disposed on a respective one of surfaces of the plurality of conductive pins away from the base.

A multichip module comprises a carrier, a plurality of chips, an electrical insulating layer, and an electrical interconnect structure. The carrier includes a bottom wall and four side walls defining an internal cavity. The chips are positioned in the internal cavity, with each chip including a plurality of bond pads. The electrical insulating layer is formed from electrically insulating material and is positioned on an upper surface of the carrier and the chips. The electrical interconnect structure includes a plurality of interconnect traces, with each interconnect trace formed from electrically conductive material and electrically connected to a first bond pad on a first chip and a second bond pad on a second chip. Each interconnect trace includes a bridge having a segment that is spaced apart from, and positioned above, the electrical insulating layer.

A semiconductor package according to the exemplary embodiments of the disclosure includes a base substrate including a base bonding pad, a first semiconductor chip disposed on the base substrate, a first adhesive layer provided under the first semiconductor chip, a first bonding pad provided in a bonding region on an upper surface of the first semiconductor chip, a first bonding wire interconnecting the base bonding pad and the first bonding pad, and a crack preventer provided in a first region at the upper surface of the first semiconductor chip. The crack preventer includes dummy pads provided at opposite sides of the first region and a dummy wire interconnecting the dummy pads.

A method for manufacturing electronic chips includes forming, on the side of a first face of a semiconductor substrate, in and on which a plurality of integrated circuits has been formed beforehand, metallizations coupling contacts of adjacent integrated circuits to one another. The method further includes forming, on the side of the first face of the substrate, first trenches extending through the first face of the substrate and laterally separating the adjacent integrated circuits. The first trenches extend through the metallizations to form at least a portion of metallizations at each of the adjacent circuits.

A bonded structure can include a first element having a first conductive interface feature and a second element having a second conductive interface feature. An integrated device can be coupled to or formed with the first element or the second element. The first conductive interface feature can be directly bonded to the second conductive interface feature to define an interface structure. The interface structure can be disposed about the integrated device in an at least partially annular profile to connect the first and second elements.

Provided is a multi-chip package in which a plurality of semiconductor chips having different sizes are stacked. A multi-chip package may include a substrate, and a plurality of semiconductor chips stacked on the substrate, each of the plurality of semiconductor chips having a different size. Each of the plurality of semiconductor chips including a pad group and a reference region associated with the pad group, each pad group having a plurality of pads, and the plurality of pads in each pad group located at same coordinates with respect to the associated reference region, and each of the plurality of semiconductor chips having their reference regions vertically aligned.

A semiconductor element including an array in which a plurality of avalanche photodiodes is arranged includes a plurality of first electrodes configured to receive supply of a first voltage to be used by the plurality of avalanche photodiodes from outside, and at least one second electrode configured to receive supply of a second voltage from outside different from the first voltage. The plurality of first electrodes and the at least one second electrode are disposed outside the array. The at least one second electrode is disposed between one and another one of the plurality of first electrodes.

A multi-chip package structure includes outer leads, a first chip and a second chip. The outer leads are disposed on four sides of a chip bonding area of a package carrier thereof, respectively. The first chip is fixed on the chip bonding area and includes a core and a seal ring. Input/output units, and first bonding pads are disposed, in an outward order, on the sides of the core. Each first bonding pad is electrically connected to a corresponding outer lead through a first wire. Dummy pads are disposed between the input/output units and the at least one side of the core. The second chip is stacked on the core and includes second bonding pads connected to the corresponding outer leads through second wires and dummy pads, so as to prevent from short circuit caused by soldering overlap and contact between the wires.