An electronic device has a display substrate including a display area, a driver area, and a fan-out area. The fan-out area has interconnects that provide electrical accesses to display elements on the display area. A driver chip is disposed on the driver area and includes a first edge adjacent to the display area, two side edges connected to the first edge, and a plurality of pad groups. Each pad group includes a row of electronic pads that are electrically coupled to a subset of display elements via a subset of interconnects routed on the fan-out area. The pad groups include a first pad group and a second pad group disposed immediately adjacent to the first pad group. A first subset of interconnects cross one of the two side edges, and extend above a gap between rows of the first and second pad groups to reach the first pad group.

An electronic device includes a first integrated circuit (IC) die and a second IC die. The first IC die includes a first set of contact pads arranged in a first geometrical pattern on a first surface of the first IC die, the second IC die includes a second set of the contact pads that are arranged, on a second surface of the second IC die, in a second geometrical pattern that is a mirror image of the first geometrical pattern. The second surface of the second IC die is facing the first surface of the first IC die, and the contact pads of the first and second sets are aligned with one another and mounted on one another.

A semiconductor package includes: a first structure having a first insulating layer disposed on one surface, and first electrode pads and first dummy pads penetrating through the first insulating layer, a second structure having a second insulating layer having the other surface bonded to the one surface and the first insulating layer and disposed on the other surface, and second electrode pads and second dummy pads that penetrate through the second insulating layer, the second electrode pads being bonded to the first electrode pads, respectively, and the second dummy pads being bonded to the first dummy pads, respectively. In the semiconductor chip, ratios of surface areas per unit area of the first and second dummy pads to the first and second insulating layers on the one surface and the other surface gradually decrease toward sides of the first and second structures.

A semiconductor structure is provided. The semiconductor structure includes a first semiconductor device. The semiconductor structure includes a first semiconductor device and a second semiconductor device. The first semiconductor device includes a first oxide layer formed below the a first substrate, a first bonding layer formed below the first oxide layer, and a first bonding via formed through the first bonding layer and the first oxide layer. The second semiconductor device includes a second oxide layer formed over a second substrate, a second bonding layer formed over the second oxide layer, and a second bonding via formed through the second bonding layer and the second oxide layer. The semiconductor structure also includes a bonding structure between the first substrate and the second substrate, and the bonding structure includes the first bonding via bonded to the second bonding via.

The disclosure provides a semiconductor chip suit for driving a display panel. The semiconductor chip includes a first pad group and a second pad group. The first pad group and the second pad group are disposed at a first long side of the semiconductor chip. The first distance from the first pad group to the edge of the first long side is different from the second distance from the second pad group to the edge of the first long side. The first pad group and the second pad group belong to a first pad row disposed at the first long side. The first pad group comprises a plurality of pads which are closer to the middle of the first pad row than the second pad group.

Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface, and a die secured to the package substrate, wherein the die has a first surface and an opposing second surface, the die has first conductive contacts at the first surface and second conductive contacts at the second surface, and the first conductive contacts are coupled to conductive pathways in the package substrate by first non-solder interconnects.

Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface, and a die secured to the package substrate, wherein the die has a first surface and an opposing second surface, the die has first conductive contacts at the first surface and second conductive contacts at the second surface, and the first conductive contacts are coupled to conductive pathways in the package substrate by first non-solder interconnects.

A chip includes: a chip substrate including a central area and an edge area surrounding the central area; and a plurality of pads arranged on the chip substrate, the plurality of pads including a first pad and a second pad, wherein the first pad is arranged in the edge area and includes at least one straight side adjacent to a side of the chip substrate, and the second pad is arranged in the central area.

A semiconductor package may include a redistribution substrate, a first semiconductor chip on the redistribution substrate, and a second semiconductor chip between the redistribution substrate and the first semiconductor chip. The second semiconductor chip may have a width in a first direction that is smaller than a width of the first semiconductor chip in the first direction. The first semiconductor chip may include a first alignment key pattern on a bottom surface thereof. The second semiconductor chip may be spaced apart from the first alignment key pattern. The second semiconductor chip may include a second interconnection layer on the bottom surface of the first semiconductor chip, a second semiconductor substrate on a bottom surface of the second interconnection layer and exposing a bottom surface of an edge region of the second interconnection layer, and a second alignment key pattern on the edge region of the second interconnection layer.

A semiconductor package includes a first semiconductor chip that has a mount region and an overhang region, a substrate disposed on a bottom surface at the mount region of the first semiconductor chip, and a molding layer disposed on the substrate. The molding layer includes a first molding pattern disposed on a bottom surface at the overhang region of the first semiconductor chip and covering a sidewall of the substrate, and a second molding pattern on the first molding pattern and covering a sidewall of the first semiconductor chip.