A package includes a chip formed in a first area of the package and a molding compound formed in a second area of the package adjacent to the first area. A first polymer layer is formed on the chip and the molding compound, a second polymer layer is formed on the first polymer layer, and a plurality of interconnect structures is formed between the first polymer layer and the second polymer layer. A metal-insulator-metal (MIM) capacitor is formed on the second polymer layer and electrically coupled to at least one of the plurality of interconnect structures. A metal bump is formed over and electrically coupled to at least one of the plurality of interconnect structures.

In an embodiment, a method includes attaching a first package component to a first carrier, the first package component comprising: an aluminum pad disposed adjacent to a substrate; a sacrificial pad disposed adjacent to the substrate, the sacrificial pad comprising a major surface opposite the substrate, a protrusion of the sacrificial pad extending from the major surface; and a dielectric bond layer disposed around the aluminum pad and the sacrificial pad; attaching a second carrier to the first package component and the first carrier, the first package component being interposed between the first carrier and the second carrier; removing the first carrier; planarizing the dielectric bond layer to comprise a top surface being coplanar with the protrusion; and etching a portion of the protrusion.

In one example, a semiconductor device can comprise (a) an electronic device comprising a device top side, a device bottom side opposite the device top side, and a device sidewall between the device top side and the device bottom side, (b) a first conductor comprising, a first conductor side section on the device sidewall, a first conductor top section on the device top side and coupled to the first conductor side section, and a first conductor bottom section coupled to the first conductor side section, and (c) a protective material covering the first conductor and the electronic device. A lower surface of the first conductor top section can be higher than the device top side, and an upper surface of the first conductor bottom section can be lower than the device top side. Other examples and related methods are also disclosed herein.

In an optical receiver circuit which suppresses an unnecessary increase in impedance and occurrences of resonance and radiation noise and which produces preferable high-frequency transmission characteristics, a PD submount mounted with a PD chip and a chip capacitor and a TIA carrier mounted with a TIA chip are electrically connected to each other by a bonding wire. The chip includes an anode electrode pad and a cathode electrode pad, anode electrode-side ground pads are formed at positions that sandwich the pad, and cathode electrode-side ground pads are formed at positions that sandwich the pad. A wire electrically connects the pad and a signal pad for input of the chip to each other, a wire electrically connects the pad and the capacitor to each other, and a wire electrically connects the pads and the pads to each other.

A package structure, a packaging method and a semiconductor device are provided. The method includes: providing a semiconductor functional structure, an interconnecting layer disposed on a surface of the semiconductor functional structure; forming an isolation layer exposing part of the interconnecting layer, the exposed part of the interconnecting layer acting as a first pad, and the first pad used for performing a first type test; after completing the first type test, forming a redistribution layer on the first pad and the isolation layer, the redistribution layer and the interconnecting layer electrically connected; and forming a first insulating layer exposing parts of the redistribution layer, the exposed parts of the redistribution layer acting as a second pad and a third pad, the second pad used for performing a second type test, and the third pad used for executing a functional interaction corresponding to contents of the second type test.

A display panel, a circuit board and a display device are provided, belonging to the field of displays. The display panel has a display region and a binding region which is at least on one side of the display region, and the display panel includes: a substrate; a plurality of signal pins on the substrate and in the binding region, the signal pins being arranged at intervals in a first direction and being connected to the circuit board; and at least one non-signal pin on the substrate and between two adjacent signal pins.

A display device includes a display panel including a display area and a pad area. The display panel includes a base substrate, a pixel, a pad group, an alignment mark, and a protective layer. The pad group includes a plurality of pads arranged in a first direction. The alignment mark is spaced apart from the pad group in the first direction. The protective layer covers the pads and the alignment mark and a plurality of openings respectively exposing upper surfaces of the pads is defined in the protective layer. Each of the pads includes at least one pad pattern, and the alignment mark is disposed in a same layer as a pad pattern spaced farthest from the base substrate among the at least one pad pattern.

A semiconductor package includes a first structure having a first insulating layer and a first bonding pad penetrating the first insulating layer, and a second structure on the first structure and having a second insulating layer bonded to the first insulating layer, a bonding pad structure penetrating the second insulating layer and bonded to the first bonding pad, and a test pad structure penetrating the second insulating layer and including a test pad in an opening penetrating the second insulating layer and having a protrusion with a flat surface, and a bonding layer filling the opening and covering the test pad and the flat surface, the protrusion of the test pad extending from a surface in contact with the bonding layer, and the flat surface of the protrusion being within the opening and spaced apart from an interface between the bonding layer and the first insulating layer.

A packaging structure, a method for manufacturing the same and a semiconductor device are provided. The packaging structure includes a redistribution layer electrically connected with an interconnection layer of a semiconductor functional structure, and an insulating layer covering and exposing part of the redistribution layer. The exposed part of the redistribution layer includes at least one first pad. The first pad includes a first area and a second area arranged continuously. The first area is configured for testing. The second area is configured for performing functional interaction corresponding to content of the test.

Embodiments described herein may be related to apparatuses, processes, and techniques related to forming capacitors using lines in a bond pad layer within hybrid bonding techniques of two separate dies and then coupling those dies. In embodiments, these techniques may involve using dummy bond pads, where the width of these dummy bond pads are smaller than that of active bond pads, to create a pattern to serve as a capacitor structure. Other embodiments may be described and/or claimed.