A method of preparing a substrate for substrate bonding is provided. The method comprises: forming a recess in a substrate surface of the substrate, and forming a bondable dielectric layer on the substrate surface of the substrate. The bondable dielectric layer has a bonding surface on an opposite side of the bondable dielectric layer to the substrate surface, wherein the recess and the bondable dielectric layer define a dielectric cavity having a dielectric cavity volume. A plug is formed configured to make electrical contact to the substrate in the dielectric cavity volume. The plug has a plug volume which is less than the dielectric cavity volume, wherein the plug extends from the dielectric cavity beyond the bonding surface in a direction generally normal to the bonding surface. The plug is coined by compressing the substrate between opposing planar surfaces such that a contact surface of the plug is made co-planar with the bonding surface.

A package structure with a wettable side surface and a manufacturing method thereof, and a vertical package module are disclosed. The package structure includes a first dielectric layer, a chip and a circuit layer. The first dielectric layer is provided with a package cavity, side wall bonding pads are arranged on a side wall of the first dielectric layer and located outside the package cavity. The chip is packaged inside the package cavity, pins of the chip face first surface of the first dielectric layer. The circuit layer is arranged on the first surface of the first dielectric layer, and the circuit layer is directly or indirectly connected to the side wall bonding pads and the pins of the chip.

Embodiments of mechanisms for testing a die package with multiple packaged dies on a package substrate use an interconnect substrate to provide electrical connections between dies and the package substrate and to provide probing structures (or pads). Testing structures, including daisy-chain structures, with metal lines to connect bonding structures connected to signals, power source, and/or grounding structures are connected to probing structures on the interconnect substrate. The testing structures enable determining the quality of bonding and/or functionalities of packaged dies bonded. After electrical testing is completed, the metal lines connecting the probing structures and the bonding structures are severed to allow proper function of devices in the die package. The mechanisms for forming test structures with probing pads on interconnect substrate and severing connecting metal lines after testing could reduce manufacturing cost.

A method includes forming an under bump metallization (UBM) layer over a dielectric layer, forming a redistribution structure over the UBM layer, disposing a semiconductor device over the redistribution structure, removing a portion of the dielectric layer to form an opening to expose the UBM layer, and forming a conductive bump in the opening such that the conductive bump is coupled to the UBM layer.

Embodiments of mechanisms for testing a die package with multiple packaged dies on a package substrate use an interconnect substrate to provide electrical connections between dies and the package substrate and to provide probing structures (or pads). Testing structures, including daisy-chain structures, with metal lines to connect bonding structures connected to signals, power source, and/or grounding structures are connected to probing structures on the interconnect substrate. The testing structures enable determining the quality of bonding and/or functionalities of packaged dies bonded. After electrical testing is completed, the metal lines connecting the probing structures and the bonding structures are severed to allow proper function of devices in the die package. The mechanisms for forming test structures with probing pads on interconnect substrate and severing connecting metal lines after testing could reduce manufacturing cost.

According to embodiments, a semiconductor device is provided. The semiconductor device includes an insulation layer, an electrode, and a groove. The insulation layer is provided on a surface of a substrate. The electrode is buried in the insulation layer, and a first end surface of the electrode is exposed from the insulation layer. The groove is formed around the electrode on the surface of the substrate. The groove has an outside surface of the electrode as one side surface, and the groove is opened on the surface side of the insulation layer. The first end surface of the electrode buried in the insulation layer protrudes from the surface of the insulation layer.

A semiconductor package includes a first semiconductor chip, a second semiconductor chip disposed on the first semiconductor chip and including a through-silicon via electrically connecting a front pad and a rear pad, a dielectric layer having a first region covering a side surface of the second semiconductor chip and a second region filling space between the first semiconductor chip and the second semiconductor chip, a first through-via penetrating through the first region of the dielectric layer, and a second through-via penetrating through the second region of the dielectric layer.

In an embodiment, a package includes a first package structure including a first die having a first active side and a first back-side, the first active side including a first bond pad and a first insulating layer a second die bonded to the first die, the second die having a second active side and a second back-side, the second active side including a second bond pad and a second insulating layer, the second active side of the second die facing the first active side of the first die, the second insulating layer being bonded to the first insulating layer through dielectric-to-dielectric bonds, and a conductive bonding material bonded to the first bond pad and the second bond pad, the conductive bonding material having a reflow temperature lower than reflow temperatures of the first and second bond pads.

An element and a bonded structure including the element are disclosed. The element can include a non-conductive region having a cavity extending at least partially through a thickness of the non-conductive region from the contact surface, and a contact feature formed in the cavity. The non-conductive region is configured to directly bond to a non-conductive region of a second element. The contact pad of the element is configured to directly bond to a contact pad of the second element. The contact pad can include a first conductive material and a second conductive material. The first conductive material can have a unit cell size greater than a unit cell size of the second conductive material. The first conductive material can be a metal alloying material. The first conductive material can be a metal silicide and the second conductive material can be a metal. A bonded conductive contact can include a conductive material and an alloying element, and an amount of the alloying element can vary through a thickness of the bonded conductive contact.

The disclosure relates to a dual-interface integrated circuit (IC) card module for use in a dual-interface IC card. Embodiments disclosed include a dual-interface integrated circuit card module (150), the module comprising: a substrate (104) having first and second opposing surfaces; a contact pad (102) on the first surface of the substrate; an integrated circuit (110) on the second surface of the substrate (104), the integrated circuit (110) having electrical connections to the contact pad (102) through the substrate (104); and a pair of antenna pads (108) disposed in recesses (103) in the second surface of the substrate (104) and electrically connected to corresponding antenna connections on the integrated circuit (110).