Patent classifications
H
ELECTRICITY
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H01
ELECTRIC ELEMENTS
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H01L
SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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2224/00
Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
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H01L2224/01
Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
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H01L2224/02
Bonding areas; Manufacturing methods related thereto
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H01L2224/07
Structure, shape, material or disposition of the bonding areas after the connecting process
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H01L2224/08
of an individual bonding area
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H01L2224/0812
the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
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H01L2224/08151
the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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H01L2224/08153
the body and the item being arranged next to each other, e.g. on a common substrate
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H01L2224/08153

ELECTRICAL BRIDGE PACKAGE WITH INTEGRATED OFF-BRIDGE PHOTONIC CHANNEL INTERFACE
20240145393 · 2024-05-02 ·

A circuit package is described that includes a photonic interposer, a second interposer, and a die partially overlapping and connected to both the photonic interposer and the second interposer.

Electrical bridge package with integrated off-bridge photonic channel interface
12191257 · 2025-01-07 · ·

A circuit package is described that includes a photonic interposer, a second interposer, and a die partially overlapping and connected to both the photonic interposer and the second interposer.