An apparatus relating generally to a substrate is disclosed. In such an apparatus, a first bond via array has first wires extending from a surface of the substrate. A second bond via array has second wires extending from the surface of the substrate. The first bond via array is disposed at least partially within the second bond via array. The first wires of the first bond via array are of a first height. The second wires of the second bond via array are of a second height greater than the first height for coupling of at least one die to the first bond via array at least partially disposed within the second bond via array.

Disclosed herein are structures and techniques related to singulation of microelectronic components with direct bonding interfaces. For example, in some embodiments, a microelectronic component may include: a surface, wherein conductive contacts are at the surface; a trench at a perimeter of the surface; and a burr in the trench.

A chip stacking and packaging structure includes a substrate, a first chip stacked on the substrate, a heat dissipation module, and a second chip stacked on the heat dissipation module. First bonding pads and second bonding pads are arranged on the substrate. First welding pins are arranged on the first chip. The first welding pins one-to-one cover and are one-to-one electrically connected to the first bonding pads. The heat dissipation module includes a first groove, a cooling liquid cavity, a liquid inlet, a liquid outlet, and first conductive columns. The first chip is embedded in the first groove. A side wall and a bottom wall of the first groove extend into the cooling liquid cavity. Each of the first conductive columns is electrically connected with a corresponding second bonding pad. Each of second welding pins of the second chip is electrically connected to a corresponding first conductive column.

A chip stacking and packaging structure includes a substrate, a first chip stacked on the substrate, a heat dissipation module, and a second chip stacked on the heat dissipation module. First bonding pads and second bonding pads are arranged on the substrate. First welding pins are arranged on the first chip. The first welding pins one-to-one cover and are one-to-one electrically connected to the first bonding pads. The heat dissipation module includes a first groove, a cooling liquid cavity, a liquid inlet, a liquid outlet, and first conductive columns. The first chip is embedded in the first groove. A side wall and a bottom wall of the first groove extend into the cooling liquid cavity. Each of the first conductive columns is electrically connected with a corresponding second bonding pad. Each of second welding pins of the second chip is electrically connected to a corresponding first conductive column.

A semiconductor package includes a first semiconductor chip including a first bonding layer, on one surface, and a chip structure stacked on the first semiconductor chip and including a second bonding layer on a surface facing the first semiconductor chip and a plurality of second semiconductor chips. The plurality of second semiconductor chips includes a chip area and a scribe area outside of the chip area, respectively, the plurality of second semiconductor chips being connected to each other by the scribe area in the chip structure. The first and second bonding layers include first and second metal pads disposed to correspond to each other and bonded to each other, respectively and first and second bonding insulating layers surrounding the first and second metal pads, respectively.

A semiconductor package includes a package substrate, first and second spacer chips attached to an upper surface of the package substrate and spaced apart from each other, a first semiconductor chip mounted on the upper surface of the package substrate and disposed between the first and second spacer chips, a plurality of second semiconductor chips sequentially stacked on the first and second spacer chips by adhesive films to cover the first semiconductor chip, and a sealing member on the package substrate and covering the first and second spacer chips, the first semiconductor chip, and the plurality of second semiconductor chips. At least a portion of the first spacer chip protrudes from one side of a lowermost second semiconductor chip among the plurality of second semiconductor chips, and the first spacer chip includes a groove at an upper surface of the protruded portion.

Disclosed herein are structures and techniques related to singulation of microelectronic components with direct bonding interfaces. For example, in some embodiments, a microelectronic component may include: a surface, wherein conductive contacts are at the surface; a trench at a perimeter of the surface; and a burr in the trench.

Disclosed herein are structures and techniques related to singulation of microelectronic components with direct bonding interfaces. For example, in some embodiments, a microelectronic component may include a surface, wherein conductive contacts are at the surface; a trench at a perimeter of the surface, the trench having a depth; and a burr in the trench having a height that is less than the depth of the trench.