A semiconductor package includes: a first wiring structure including a first wiring layer, and a second wiring layer disposed on the first wiring layer, and connected to a first connecting structure placed disposed on the first wiring layer; a first semiconductor chip disposed on the first wiring structure and connected to the first wiring structure through a first connecting pad disposed on a first side of the first semiconductor chip; a second wiring structure disposed on the first semiconductor chip; and an insulating member disposed between the first and second wiring structures, wherein the first wiring structure further includes a first signal pattern that is electrically connected to the first connecting pad, and the first signal pattern redistributes the first connecting pad to the first connecting structure via the insulating member.

Disclosed herein are cavity structures in integrated circuit (IC) package supports, as well as related methods and apparatuses. For example, in some embodiments, an IC package support may include: a cavity in a dielectric material, wherein the cavity has a bottom and sidewalls; conductive contacts at the bottom of the cavity, wherein the conductive contacts include a first material; a first peripheral material outside the cavity, wherein the first peripheral material is at the sidewalls of the cavity and proximate to the bottom of the cavity, and the first peripheral material includes the first material; and a second peripheral material outside the cavity, wherein the second peripheral material is at the sidewalls of the cavity and on the first peripheral material, and the second peripheral material is different than the first peripheral material.

A high voltage semiconductor package includes a semiconductor device. The semiconductor device includes a high voltage semiconductor transistor chip having a front side and a backside. A low voltage load electrode and a control electrode are disposed on the front side of the semiconductor transistor chip. A high voltage load electrode is disposed on the backside of the semiconductor transistor chip. The semiconductor package further includes a dielectric inorganic substrate. The dielectric inorganic substrate includes a pattern of first metal structures running through the dielectric inorganic substrate and connected to the low voltage load electrode, and at least one second metal structure running through the dielectric inorganic substrate and connected to the control electrode. The front side of the semiconductor transistor chip is attached to the dielectric inorganic substrate by a wafer bond connection, and the dielectric inorganic substrate has a thickness of at least 50 μm.

A package assembly includes a substrate and at least a first die having a first contact array and a second contact array. First and second via assemblies are respectively coupled with the first and second contact arrays. Each of the first and second via assemblies includes a base pad, a cap assembly, and a via therebetween. One or more of the cap assembly or the via includes an electromigration resistant material to isolate each of the base pad and the cap assembly. Each first cap assembly and via of the first via assemblies has a first assembly profile less than a second assembly profile of each second cap assembly and via of the second via assemblies. The first and second cap assemblies have a common applied thickness in an application configuration. The first and second cap assemblies have a thickness variation of ten microns or less in a reflowed configuration.

Representative implementations of techniques and devices are used to reduce or prevent conductive material diffusion into insulating or dielectric material of bonded substrates. Misaligned conductive structures can come into direct contact with a dielectric portion of the substrates due to overlap, especially while employing direct bonding techniques. A barrier interface that can inhibit the diffusion is disposed generally between the conductive material and the dielectric at the overlap.

A package structure includes a base material, at least one electronic device, at least one encapsulant and a plurality of dummy pillars. The electronic device is electrically connected to the base material. The encapsulant covers the electronic device. The dummy pillars are embedded in the encapsulant. At least two of the dummy pillars have different heights.

Disclosed are semiconductor packages and methods of fabricating the same. The semiconductor package includes a redistribution substrate that includes a chip region and an edge region around the chip region, and a semiconductor chip on the chip region of the redistribution substrate. The redistribution substrate includes a plurality of dielectric layers that are vertically stacked, a plurality of redistribution patterns on the chip region and in each of the dielectric layers, and a redistribution test pattern on the edge region and at a level the same as a level of at least one of the redistribution patterns.

Embodiments described herein provide techniques for testing a semiconductor package by using a diode to couple a test pad to a contact pad. In one scenario, a package comprises a die stack comprising one or more dies and a molding compound encapsulating the die stack. In this package, a substrate is over the molding compound. Also, a test pad and a contact pad are on a surface of the substrate. The contact pad is coupled to the die stack. A diode couples the test pad to the contact pad. In one example, the test pad is coupled to a P side of the diode's P-N junction and the contact pad is coupled to an N side of the diode's P-N junction. In operation, current can flow from the test pad through the contact pad (and the die stack), but current cannot flow from the contact pad through the test pad.

A microelectronic assembly is provided, comprising: a first integrated circuit (IC) die at a first level, a second IC die at a second level, and a third IC die at a third level, the second level being in between the first level and the third level. A first interface between the first level and the second level is electrically coupled with high-density interconnects of a first pitch and a second interface between the second level and the third level is electrically coupled with interconnects of a second pitch. In some embodiments, at least one of the first IC die, second IC die, and third IC die comprises another microelectronic assembly. In other embodiments, at least one of the first IC die, second IC die, and third IC die comprises a semiconductor die.

A semiconductor package includes a semiconductor chip including a connecting pad, a mold layer covering the semiconductor chip, a lower redistribution layer on the semiconductor chip and the mold layer, and a connecting terminal on the lower redistribution layer. The lower redistribution layer includes a first lower insulating layer, a first conformal redistribution pattern extending through the first lower insulating layer, a second lower insulating layer on the first lower insulating layer and the first conformal redistribution pattern, and a first filled redistribution pattern disposed on the first conformal redistribution pattern and extending through the second lower insulating layer. A side surface of the first filled redistribution pattern is spaced apart from an inner side surface of the first conformal redistribution pattern. The second lower insulating layer is between the inner side surface of the first conformal redistribution pattern and the side surface of the first filled redistribution pattern.