In embodiments, a semiconductor package may include a first die and a second die. The package may additionally include a serializer/deserializer (SerDes) die coupled with the first and the second dies. The SerDes die may be configured to serialize signals transmitted from the first die to the second die, and deserialize signals received from the second die. Other embodiments may be described and/or claimed.

A semiconductor storage device includes first and second chips and first and second power supply electrodes. The first chip includes conductive layers arranged in a first direction, a semiconductor pillar extending in the first direction and facing the conductive layers, first contacts extending in the first direction and connected to the conductive layers, second contacts extending in the first direction and connected to a first power supply electrode, third contacts extending in the first direction, facing the second contacts in a direction crossing the first direction, and connected to the second power supply electrode, and first bonding electrodes connected to the first contacts. The second chip includes a semiconductor substrate, transistors provided on the semiconductor substrate, fourth contacts connected to the transistors, and second bonding electrodes connected to the fourth contacts. The first and second chips are bonded together so that respective first and second bonding electrodes are connected together.

A semiconductor package includes a package substrate having a first side portion adjacent to a first edge, and a second side portion adjacent to a second edge opposite the first edge; a plurality of first substrate pads on the package substrate at the first side portion of the package substrate; a first chip on the package substrate; a second chip stacked on the first chip in a step-wise manner to result in a first exposure region exposing a portion of a surface of the first chip with respect to the second chip due to the step-wise stacking, the first exposure region being adjacent to a first edge of the first chip; a plurality of first bonding pads on a first portion of the first exposure region, the first portion of the first exposure region being adjacent to the first edge of the first chip; a plurality of second bonding pads on a second portion of the first exposure region, the second portion of the first exposure region further from the first edge of the first chip than the first portion of the first exposure region is to the first edge of the first chip, the plurality of second bonding pads being electrically insulated from any circuit components in the first chip; a plurality of third bonding pads on a surface of the second chip; and a plurality of bonding wires electrically connecting the third bonding pads to the first substrate pads via the second bonding pads.

A semiconductor memory device includes first column line pads, having a longer width and a shorter width, defined on one surface of a cell wafer, and coupled to a memory cell array of the cell wafer; second column line pads, having a longer width and a shorter width, defined on one surface of a peripheral wafer that is bonded to the one surface of the cell wafer, coupled to a page buffer circuit of the peripheral wafer, and bonded respectively to the first column line pads; first row line pads defined on the one surface of the cell wafer, and coupled to the memory cell array; and second row line pads defined on the one surface of the peripheral wafer, coupled to a row decoder of the peripheral wafer, and bonded respectively to the first row line pads. The longer widths of the first and second column line pads and the longer widths of the first and second row line pads extend in the same direction.

A semiconductor storage device includes first and second chips and first and second power supply electrodes. The first chip includes conductive layers arranged in a first direction, a semiconductor pillar extending in the first direction and facing the conductive layers, first contacts extending in the first direction and connected to the conductive layers, second contacts extending in the first direction and connected to a first power supply electrode, third contacts extending in the first direction, facing the second contacts in a direction crossing the first direction, and connected to the second power supply electrode, and first bonding electrodes connected to the first contacts. The second chip includes a semiconductor substrate, transistors provided on the semiconductor substrate, fourth contacts connected to the transistors, and second bonding electrodes connected to the fourth contacts. The first and second chips are bonded together so that respective first and second bonding electrodes are connected together.

An alignment carrier, assembly and methods that enable the precise alignment and assembly of two or more semiconductor die using an interconnect bridge. The alignment carrier includes a substrate composed of a material that has a coefficient of thermal expansion that substantially matches that of an interconnect bridge. The alignment carrier further includes a plurality of solder balls located on the substrate and configured for alignment of two or more semiconductor die.

Disclosed herein are microelectronic assemblies including direct bonding, as well as related structures and techniques. For example, in some embodiments, a microelectronic assembly may include a first microelectronic component and a second microelectronic component coupled to the first microelectronic component by a direct bonding region, wherein the direct bonding region includes a first subregion and a second subregion, and the first subregion has a greater metal density than the second subregion. In some embodiments, a microelectronic assembly may include a first microelectronic component and a second microelectronic component coupled to the first microelectronic component by a direct bonding region, wherein the direct bonding region includes a first metal contact and a second metal contact, the first metal contact has a larger area than the second metal contact, and the first metal contact is electrically coupled to a power/ground plane of the first microelectronic component.

A radio frequency module includes a mounting substrate including a first main surface and a second main surface opposite to the first main surface. A first electronic component is disposed on the first main surface of the mounting substrate. A second electronic component is disposed on the second main surface of the mounting substrate. A plurality of connection terminals are disposed on the second main surface of the mounting substrate. A wiring layer faces the second main surface of the mounting substrate. The wiring layer includes a plurality of external connection electrodes, each connected to at least one of the second electronic component and the plurality of connection terminals. At least one of the plurality of external connection electrodes overlaps the second electronic component when viewed in plan in a thickness direction of the substrate.

A semiconductor memory device includes first column line pads, having a longer width and a shorter width, defined on one surface of a cell wafer, and coupled to a memory cell array of the cell wafer; second column line pads, having a longer width and a shorter width, defined on one surface of a peripheral wafer that is bonded to the one surface of the cell wafer, coupled to a page buffer circuit of the peripheral wafer, and bonded respectively to the first column line pads; first row line pads defined on the one surface of the cell wafer, and coupled to the memory cell array; and second row line pads defined on the one surface of the peripheral wafer, coupled to a row decoder of the peripheral wafer, and bonded respectively to the first row line pads. The longer widths of the first and second column line pads and the longer widths of the first and second row line pads extend in the same direction.

A multi-chip module includes a first semiconductor component including a first set of connections having a first pitch dimension and at least a second set of connections having a second pitch dimension, wherein the first pitch dimension is smaller than the second pitch dimension. The multi-chip module further includes a second semiconductor component interconnected with the first set of connections of the first semiconductor component. The multi-chip module further includes at least a third semiconductor component interconnected with the second set of connections of the first semiconductor component and wherein a surface of the third semiconductor component is adhered to a surface of the second semiconductor component, wherein the surfaces at least partially overlap one another.