A method for manufacturing a three-dimensional integrated circuit includes attaching a first side of a first die to a first carrier wafer. The method includes preparing a second side of the first die to generate a prepared second side of the first die. The method includes attaching the prepared second side of the first die to a second carrier wafer. The method includes removing the first carrier wafer from the first side of the first die to form a transitional three-dimensional integrated circuit. The method includes attaching a third carrier wafer to a first side of the transitional three-dimensional integrated circuit. The method includes attaching a first side of the second die to a second side of the transitional three-dimensional integrated circuit.

A chip structure has a chip body having a plurality of pads, a plurality of metal bumps respectively formed on the pads, and a patterned bump directly formed on the chip body. The patterned bump has at least two different upper and lower plane patterns. A top surface of each of the metal bumps is higher than a height position on which the upper plane pattern is. When the chip structure is ground to the height position, the ground tops of the metal bumps and the upper plane pattern are flush. Therefore, detecting whether the upper plane pattern is exposed determines whether all the metal bumps are exposed and flush to each other to avoid insufficient grinding depth or over-ground.

A three-dimensional integrated circuit includes a first die having a first geometry. The first die includes a first region that operates with a first power density and a second region that operates with a second power density. The first power density is less than the second power density. The first die includes first electrical contacts disposed in the first region on a first side of the first die along a periphery of the first die. The three-dimensional integrated circuit includes a second die having a second geometry. The second die includes second electrical contacts disposed on a first side of the second die. A stacked portion of the second die is stacked within the periphery of the first die and an overhang portion of the second die extends beyond the periphery of the first die. The second electrical contacts are aligned with and coupled to the first electrical contacts.

A three-dimensional integrated circuit includes a first die having a first geometry. The first die includes a first region that operates with a first power density and a second region that operates with a second power density. The first power density is less than the second power density. The first die includes first electrical contacts disposed in the first region on a first side of the first die along a periphery of the first die. The three-dimensional integrated circuit includes a second die having a second geometry. The second die includes second electrical contacts disposed on a first side of the second die. A stacked portion of the second die is stacked within the periphery of the first die and an overhang portion of the second die extends beyond the periphery of the first die. The second electrical contacts are aligned with and coupled to the first electrical contacts.

A semiconductor device includes a substrate, a semiconductor chip having a first surface bonded to the substrate and a second surface that is opposite to the first surface and includes a first electrode pad and a second electrode pad thereon, the first electrode pad being electrically connected to a circuit of the semiconductor chip that is operated during operation of the semiconductor device and the second electrode pad being electrically separated from the circuit, a first wire extending between the first electrode pad and a terminal of the substrate that is electrically connected with an external device during operation of the semiconductor device, a second wire extending between the second electrode pad and the substrate, and a resin layer formed over the second surface of the semiconductor chip and covering the first and second wires.

A semiconductor package includes a lower semiconductor chip, a first upper semiconductor chip including upper pads, and bonding wires coupled to the substrate and the upper pads. The first upper semiconductor chip has a first overhang region adjacent to a first lateral surface of the first upper semiconductor chip, a second overhang region adjacent to a second lateral surface of the first upper semiconductor chip, and a first corner overhang region adjacent to a corner where the first and second lateral surfaces meet with each other. The upper pads include first upper pads on the first overhang region and second upper pads on the second overhang region. The number of the first upper pads is less than that of the second upper pads. The upper pads are spaced apart from the first corner overhang region.

Disclosed are semiconductor packages and their fabrication methods. The semiconductor package comprises semiconductor chips stacked on a substrate and including first and second pads on top surfaces thereof, and bonding wires connecting the first and second pads to the substrate. The semiconductor chips alternately protrude in a first direction and its opposite direction. The semiconductor chip has a first lateral surface spaced apart from another semiconductor chip. The top surface of the semiconductor chip is provided thereon with a first arrangement line extending along the first lateral surface and with second arrangement lines extending from opposite ends of the first arrangement line. Wherein as a distance between the first and second arrangement lines increases, a distance between the second arrangement lines and the first lateral surface increases. The first pads are arranged along the first arrangement line. The second pads are arranged along the second arrangement lines.

Disclosed are semiconductor packages and their fabrication methods. The semiconductor package comprises semiconductor chips stacked on a substrate and including first and second pads on top surfaces thereof, and bonding wires connecting the first and second pads to the substrate. The semiconductor chips alternately protrude in a first direction and its opposite direction. The semiconductor chip has a first lateral surface spaced apart from another semiconductor chip. The top surface of the semiconductor chip is provided thereon with a first arrangement line extending along the first lateral surface and with second arrangement lines extending from opposite ends of the first arrangement line. Wherein as a distance between the first and second arrangement lines increases, a distance between the second arrangement lines and the first lateral surface increases. The first pads are arranged along the first arrangement line. The second pads are arranged along the second arrangement lines.

A semiconductor package comprises a first die having a central region and a peripheral region that surrounds the central region; a plurality of through electrodes that penetrate the first die; a plurality of first pads at a top surface of the first die and coupled to the through electrodes; a second die on the first die; a plurality of second pads at a bottom surface of the second die, the bottom surface of the second die facing the top surface of the first die; a plurality of connection terminals that connect the first pads to the second pads; and a dielectric layer that fills a space between the first die and the second die and surrounds the connection terminals. A first width of each of the first pads in the central region may be greater than a second width of each of the first pads in the peripheral region. Each of the connection terminals may include a convex portion at a lateral surface thereof, which protrudes beyond a lateral surface of a respective first pad and a lateral surface of a respective second pad. The convex portion may protrude in a direction away from a center of the first die. Protruding distances of the convex portions may increase in a direction from the center of the first die toward an outside of the first die.

A chip structure has a chip body having a plurality of pads, a plurality of metal bumps respectively formed on the pads, and a patterned bump directly formed on the chip body. The patterned bump has at least two different upper and lower plane patterns. A top surface of each of the metal bumps is higher than a height position on which the upper plane pattern is. When the chip structure is ground to the height position, the ground tops of the metal bumps and the upper plane pattern are flush. Therefore, detecting whether the upper plane pattern is exposed determines whether all the metal bumps are exposed and flush to each other to avoid insufficient grinding depth or over-ground.