A semiconductor structure includes a semiconductor substrate; a first pad and a second pad on a first top surface of the semiconductor substrate; a circuit board including a second top surface, a recess indented from the second top surface into the circuit board, a polymeric pad disposed on the second top surface and corresponding to the first pad, and an active pad disposed within the recess and corresponding to the second pad; a first bump disposed between and contacting the polymeric pad and the first pad; and a second bump disposed between and contacting the active pad and the second pad, wherein a height of the first bump is substantially shorter than a height of the second bump.

A method and apparatus for laterally urging two semiconductor chips, dies or wafers into an improved state of registration with each other, the method and apparatus employing microstructures comprising: a first microstructure disposed on a first major surface of a first one of said two semiconductor chips, dies or wafers, wherein the first microstructure includes a sidewall which is tapered thereby disposing it at an acute angle compared to a perpendicular of said first major surface, and a second microstructure disposed on a first surface of a second one of said two semiconductor chips, dies or wafers, wherein the shape of the second microstructure is complementary to, and mates with or contacts, in use, the first microstructure, the second microstructure including a surface which contacts said sidewall when the first and second microstructures are mated or being mated, the sidewall of the first microstructure and the surface of the second microstructure imparting a lateral force for urging the two semiconductor chips, dies or wafers into said improved state of registration.

A die stack that includes a first chip die, a second chip die connected to the first chip die by one or more controlled collapse chip connection (“C4”) solder bump bonds, and a spacer die interposed between the first and second chip dies. The spacer die includes through holes for the one or more C4 solder bumps, and has a thickness such that when the first and second chip dies are compressed into contact with the spacer die, the spacer die thickness is a minimum defined spacing between the first and second chip dies, and the spacer die operates as a hard stop against compression of the die stack after the first and second chip dies are compressed into contact with the spacer die.

A semiconductor device includes a semiconductor chip and a metal plate. The semiconductor chip has first and second surfaces, four side surface, four corners, four sides. The four side surfaces connect the first surface and the second surface. Two of the four side surfaces contact each other at one of the four corners. The four side surfaces contact the second surface at the four sides. The first and second electrodes are provided at the first front side. The metal plate is connected to the second surface side of the semiconductor chip. The metal plate includes third and fourth surfaces, and a through-hole or a notch. The third surface is connected to the second surface of the semiconductor chip. The fourth surface is provided at a side opposite to the third surface. The through-hole or the notch extends through the metal plate from the fourth surface to the third surface.

A semiconductor package includes a package substrate and a semiconductor chip mounted on the package substrate. The package substrate includes a signal bump land and an anchoring bump land, and the semiconductor chip includes a signal bump and an anchoring bump. The signal bump is bonded to the signal bump land, the anchoring bump is disposed to be adjacent to the anchoring bump land, and a bottom surface of the anchoring bump is located at a level which is lower than a top surface of the anchoring bump land with respect to a surface of the package substrate.

The present application provides a semiconductor device. The semiconductor device includes a bonding pad disposed over a semiconductor substrate; a first spacer disposed over a top surface of the bonding pad; a second spacer disposed over a sidewall of the bonding pad; a dielectric layer between the bonding pad and the semiconductor substrate. The dielectric layer includes silicon-rich oxide; and a conductive bump disposed over the first passivation layer. The conductive bump is electrically connected to a source/drain (S/D) region in the semiconductor substrate through the bonding pad. The semiconductor device also includes a dielectric liner disposed between the first spacer and the bonding pad; and a first passivation layer covering the second spacer, wherein the dielectric liner is L-shaped, and the first spacer is separated from the bonding pad by the dielectric liner.

A data storage device includes a substrate and one or more grid array integrated circuit packages. The grid array integrated circuit package includes at least one self-alignment pin having a tapered shape. The substrate includes one or more connection pads to receive the grid array integrated circuit packages. The connection pads include at least one self-alignment receptacle that receives the self-alignment pins such that the grid array integrated circuit packages maintain an alignment with an associated connection pad of the substrate.

An interconnection technology may use molded solder to define solder balls. A mask layer may be patterned to form cavities and solder paste deposited in the cavities. Upon heating, solder balls are formed. The cavity is defined by spaced walls to keep the solder ball from bridging during a bonding process. In some embodiments, the solder bumps connected to the solder balls may have facing surfaces which are larger than the facing surfaces of the solder ball.

A semiconductor device includes a first semiconductor substrate, a second semiconductor substrate, a bonding electrode, and a dummy electrode. The first semiconductor substrate has a first surface and a first wiring, and contains a first semiconductor material. The second semiconductor substrate has a second surface and a second wiring, and contains a second semiconductor material, and the first surface and the second surface face each other. The bonding electrode is arranged between the first surface and the second surface, and is electrically connected to the first wiring and the second wiring. The dummy electrode is arranged between the first surface and the second surface, and is electrically insulated from at least one of the first wiring and the second wiring. The bonding electrode has a bonding bump and a first bonding pad. The dummy electrode has a dummy bump and a first dummy pad.

A semiconductor device includes a first substrate, a second substrate, a connection part, and an alignment mark. The connection part includes a first electrode which is disposed on the first substrate, a second electrode which is disposed on the second substrate, and a connection bump which connects the first electrode and the second electrode. The alignment mark includes a first mark which is disposed on the first substrate and a second mark which is disposed on the second substrate. A sum of a height of the first mark and a height of the second mark is substantially equal to a sum of a height of the first electrode, a height of the second electrode, and a height of the connection bump.