A multi-layered structure interface between a ball grid array (BGA) device and a printed circuit board (PCB), including a ball guide layer comprising a through hole; a first elastomeric portion of a first layer in superimposition with at least a portion of the through hole, the first elastomeric portion having a first width; and a second elastomeric portion of a second layer having a second width; wherein first elastomeric portion is positioned between the through hole of the ball guide layer and the second elastomeric portion, wherein the first width of the first elastomeric portion is greater than the second width of the second elastomeric portion.

A semiconductor device includes a power semiconductor device, a circuit board, and an insulating substrate. The power semiconductor device includes contact pads. Adjacent ones of the contact pads are separated by one of a plurality of gaps. The circuit board includes traces for coupling with the contact pads of the power semiconductor device. The contact pads are physically attached to the traces. The insulating substrate is disposed between the circuit board and the power semiconductor device, where portions of the insulating substrate are disposed in the plurality of gaps, and where the insulating substrate has a monolithic structure.

A method of manufacturing a three-dimensional semiconductor device includes forming a bi-layer sacrificial stack on a top wafer and a bottom wafer each including a series of interconnects in a dielectric substrate. The bi-layer sacrificial stack includes a second sacrificial layer on a first sacrificial layer. The method also includes selectively etching the second sacrificial layers to form a first pattern of projections on the top wafer and a second pattern of projections on the bottom wafer. The first pattern of projections is configured to mesh with the second pattern of projections. The method also includes positioning the top wafer on the bottom wafer and releasing the top wafer such that engagement between the first pattern of projections and the second pattern of projections self-aligns the plurality of interconnects of the top wafer with the plurality of interconnects of the bottom wafer within a misalignment error.

In an embodiment a method includes providing a semiconductor chip having a plurality of contact pins, at least one positioning pin and an underside, wherein the contact pins and the positioning pin protrude from the underside, respectively, wherein the contact pins are configured for making electrical contact with the semiconductor chip, wherein the positioning pin narrows in a direction away from the underside, and wherein the positioning pin protrudes further from the underside than the contact pins, providing a connection carrier having a plurality of contact recesses, at least one positioning recess and an upper side, wherein each contact recess is at least partially filled with a solder material, heating the solder material in the contact recesses to a joining temperature at which the solder material at least partially melts and placing the semiconductor chip on the connection carrier, wherein each contact pin is inserted into a contact recess and the positioning pin is inserted into the positioning recess.

A semiconductor chip including a semiconductor substrate having a first surface and a second surface and having an active layer in a region adjacent to the first surface, a first through electrode penetrating at least a portion of the semiconductor substrate and connected to the active layer, a second through electrode located at a greater radial location from the center of the semiconductor substrate than the first through electrode, penetrating at least a portion of the semiconductor substrate, and connected to the active layer. The semiconductor chip also including a first chip connection pad having a first height and a first width, located on the second surface of the semiconductor substrate, and connected to the first through electrode, and a second chip connection pad having a second height greater than the first height and a second width greater than the first width, located on the second surface of the semiconductor substrate, and connected to the second through electrode.

An electronic component is provided that includes a first die, a support with a die-attachment surface and a die-aligning element that is adjacent to the die-attachment surface. The die aligning element includes a first die-alignment wall. Moreover, a first side of the first die is horizontally fixed to the first die-alignment wall with a die-attach material. The side of the first die that is opposite to the first side of the first die is horizontally unfixed.

A semiconductor assembly packaging method, a semiconductor assembly and an electronic device are provided. The method comprises providing an interconnect board and at least one semiconductor device; aligning and attaching the at least one semiconductor device to the interconnect board by forming a plurality of alignment solder joints; applying pressure to the at least one semiconductor device and/or the interconnect board while the alignment solder joints are in a molten or partially molten state, whereby first connection terminals on the interconnect board are joined with and bonded to corresponding second connection terminals on the at least one semiconductor device. Using the packaging method, the semiconductor device and the interconnect board can be aligned accurately using relatively simple and low cost processes and equipment. The method can also be used to align and bond at least one semiconductor device to another semiconductor device.

A semiconductor chip including a semiconductor substrate having a first surface and a second surface and having an active layer in a region adjacent to the first surface, a first through electrode penetrating at least a portion of the semiconductor substrate and connected to the active layer, a second through electrode located at a greater radial location from the center of the semiconductor substrate than the first through electrode, penetrating at least a portion of the semiconductor substrate, and connected to the active layer. The semiconductor chip also including a first chip connection pad having a first height and a first width, located on the second surface of the semiconductor substrate, and connected to the first through electrode, and a second chip connection pad having a second height greater than the first height and a second width greater than the first width, located on the second surface of the semiconductor substrate, and connected to the second through electrode.

A semiconductor package structure includes a first package, a second package over the first package, a plurality of connectors between the first package and the second package and a plurality of baffle structures between the first package and the second package. The second package includes a bonding region and a periphery region surrounding the bonding region. The connectors are disposed in the bonding region to provide electrical connections between the first package and the second package. The baffle structures are disposed in the periphery region and are separated from each other.

A mixed-orientation multi-die (“MOMD”) integrated circuit package includes dies mounted in different physical orientations. An MOMD package includes both (a) one or more dies horizontally-mounted dies (HMDs) mounted horizontally to a horizontally-extending die mount base and (b) one or more vertically-mounted dies (VMDs) mounted vertically to the horizontally-extending die mount base. HMDs may include FPGAs or other high performance chips, while VMDs may include low performance chips and other physical structures such as heat dissipators, memory, high voltage/analog devices, sensors, or MEMS, for example. The die mount base of an MOMD package may include structures for aligning and mounting VMD(s), for example, VMD slots for receiving each mounted VMD, and VMD alignment structures that facilitate aligning and/or guiding a vertical mounting of each VMD to the die mount base. MOMD packages may provide a reduced lateral footprint and increased die integration per unit area, as compared with conventional multi-die packages.